W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 127

• Manufacturer Part Number: W83627UHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627UHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V, 5V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

This register reflects the UART interrupt status.
DEFAULT
Bit
10.2.6 Interrupt Status Register (ISR) (Read only)
3
0
0
0
1
0
NAME
BIT
7-6
5
4
3
2
1
0
BIT
BIT 7
Bit
2
0
1
1
1
0
ISR
0
1
1
FIFOS ENABLED. Set to logical 1 when UFR, bit 0 = 1.
0
0
INTERRUPT STATUS BIT 2. In 16450 mode, this bit is logical 0. In 16550 mode, bits 3
and 2 are set to logical 1 when a time-out interrupt is pending. Please see the table
below.
INTERRUPT STATUS BIT 1.
INTERRUPT STATUS BIT 0.
0 IF INTERRUPT PENDING. This bit is logic 1 if there is no interrupt pending. If one of
the interrupt sources has occurred, this bit is set to logical 0.
Bit
1
0
1
0
0
1
FIFOS ENABLED
Bit
0
1
0
0
0
0
7
0
Interrupt
priority
First
Second
Second
Third
BIT 6
-
1
0
1
6
0
UART Receive
Status
RBR Data Ready
FIFO Data Timeout
TBR Empty
Interrupt Type
5
0
-
INTERRUPT SET AND FUNCTION
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
4
0
DESCRIPTION
-112-
Interrupt Source
No Interrupt pending
1. OER = 1
3. NSER = 1 4. SBD = 1
1. RBR data ready
2. FIFO interrupt active level
Data present in RX FIFO for 4
characters period of time since last
access of RX FIFO.
TBR empty
reached
INTERRUPT
STATUS
BIT 2
3
0
These two bits identify the priority level of
the pending interrupt, as shown in the table
below.
2. PBER =1
Publication Release Date: March 24, 2008
INTERRUPT
STATUS
04
08
14
BIT 1
2
0
INTERRUPT
W83627UHG
STATUS
Clear Interrupt
Read USR
1. Read RBR
2. Read RBR until FIFO
data under active level
Read RBR
1. Write data into TBR
2. Read ISR (if priority is
BIT 0
1
0
third)
Revision 1.44
-
INTERRUPT
PENDING
0 IF
0
1