W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 164

• Manufacturer Part Number: W83627UHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627UHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V, 5V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CR 25h. (Interface Tri-state Enable; Default 00h)
CR 26h. (Global Option; Default 0s000000b)
Disable FDC interface
Pin 17
Pin 18
7~6
2~1
BIT
BIT
5
4
3
0
7
6
5
4
3
2
Reserved.
Reserved.
Reserved.
Reserved.
READ / WRITE
READ / WRITE
RIF#
GP60
R / W
R / W
R / W
R / W
R / W
R / W
R / W
R / W
UARTBTRI =>
=0 Tri-state disabled
=1 Tri-state enabled
UARTATRI =>
=0 Tri-state disabled
=1 Tri-state enabled
PRTTRI =>
=0 Tri-state disabled
=1 Tri-state enabled
FDCTRI. =>
=0 Tri-state disabled
=1 Tri-state enabled
HEFRAS =>
= 0 Write 87h to location 2E twice.
= 1 Write 87h to location 4E twice.
The corresponding power-on strapping pin is RTSA# (Pin 51).
LOCKREG =>
= 0 Enable R/W configuration registers.
= 1 Disable R/W configuration registers.
DSFDLGRQ =>
= 0 Enable FDC legacy mode for IRQ and DRQ selection. Then DO
register (base address + 2) bit 3 is effective when selecting IRQ.
= 1 Disable FDC legacy mode for IRQ and DRQ selection. Then DO
register (base address + 2) bit 3 is not effective when selecting IRQ.
DSPRLGRQ =>
= 0 Enable PRT legacy mode for IRQ and DRQ selection. Then DCR
register (base address + 2) bit 4 is effective when selecting IRQ.
= 1 Disable PRT legacy mode for IRQ and DRQ selection. Then DCR
register (base address + 2) bit 4 is not effective when selecting IRQ.
-149-
s: value by strapping
Enable FDC interface
Pin 17
Pin 18
DESCRIPTION
DESCRIPTION
HEAD#
DSKCHG#
Publication Release Date: March 24, 2008
W83627UHG
Revision 1.44