W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 163

• Manufacturer Part Number: W83627UHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627UHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V, 5V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CR 24h. (Global Option; Default 0100_0ss0b)
Note1:
Disable FDC interface
Pin 5
Pin 6
Pin 7
Pin 8
Pin 9
Pin 10
Pin 11
Pin 13
Pin 14
Pin 15
Pin 16
BIT
BIT
0
7
6
5
4
3
2
1
0
Reserved.
Reserved.
Reserved.
CTSF#
GP64
DSRF#
RTSF#
DTRF#
READ / WRITE
READ / WRITE
SOUTF
SINF
DCDF#
GP63
GP62
GP61
Read Only
R / W
R / W
R / W
R / W
R / W
IPD (Immediate Power Down). When set to 1, the whole chip is put into
power-down mode immediately.
CLKSEL => Input clock rate selection
= 0 The clock input on pin 18 is 24 MHz.
= 1 The clock input on pin 18 is 48 MHz. (Default)
Select output type of SYSFANOUT
=0 SYSFANOUT is Open-drain. (Default)
=1 SYSFANOUT is Push-pull.
Select output type of CPUFANOUT0
=0 CPUFANOUT is Open-drain. (Default)
=1 CPUFANOUT is Push-pull.
ENKBC => Enable keyboard controller
= 0 KBC is disabled after hardware reset.
= 1 KBC is enabled after hardware reset.
This bit is read-only, and it is set or reset by a power-on strapping pin (Pin
54, SOUTA).
ENFDC => Enable FDC interface
= 0 FDC is enabled after hardware reset.
= 1 FDC is disabled after hardware reset.
This bit is set or reset by a power-on strapping pin (Pin 52, DTRA#).
Note 1
-148-
Enable FDC interface
Pin 5
Pin 6
Pin 7
Pin 8
Pin 9
Pin 10
Pin 11
Pin 13
Pin 14
Pin 15
Pin 16
DESCRIPTION
DESCRIPTION
s: value by strapping
DRVDEN0
INDEX#
MOA#
DSA#
DIR#
WD#
STEP#
WE#
TRAK0#
WP#
RDATA#
Publication Release Date: March 24, 2008
W83627UHG
Revision 1.44