W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 120

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W83627UHG

Manufacturer Part Number
W83627UHG
Description
IC I/O CONTROLLER 128-QFP
Manufacturer
Nuvoton Technology Corporation of America
Datasheets

Specifications of W83627UHG

Applications
PC's, PDA's
Interface
LPC
Voltage - Supply
3.3V, 5V
Package / Case
128-XFQFN
Mounting Type
Surface Mount
Pin Count
128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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In the PS/2 Model 30 mode, the bit definitions are as follows:
DEFAULT
NAME
BIT
BIT
7-3
0
2
1
0
BIT
DRATE 0.
RESERVED. Should be set to 0.
NOPREC. Disables the precompensation function. This bit can be set by the software.
DRATE1.
DRATE0.
NA
7
NA
6
RESERVED
NA
5
DESCRIPTION
DESCRIPTION
-105-
NA
4
how the settings correspond to individual
data rates.
Select the data rate of the FDC. See DR
register bits 1 and 0 (Data Rate Register
(DR Register) (Write base address + 4)) for
how the settings correspond to individual
data rates.
NA
3
Publication Release Date: March 24, 2008
NOPREC
2
0
W83627UHG
DRATE1
1
1
Revision 1.44
DRATE0
0
0

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