W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 137

no-image

W83627UHG

Manufacturer Part Number
W83627UHG
Description
IC I/O CONTROLLER 128-QFP
Manufacturer
Nuvoton Technology Corporation of America
Datasheets

Specifications of W83627UHG

Applications
PC's, PDA's
Interface
LPC
Voltage - Supply
3.3V, 5V
Package / Case
128-XFQFN
Mounting Type
Surface Mount
Pin Count
128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
W83627UHG
Manufacturer:
FENGHUA
Quantity:
40 000
Part Number:
W83627UHG
Manufacturer:
Winbond
Quantity:
1 000
Part Number:
W83627UHG
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
Part Number:
W83627UHG
Manufacturer:
WINBOND/华邦
Quantity:
20 000
Company:
Part Number:
W83627UHG
Quantity:
68
This mode is defined only for the forward direction. Bytes written or DMAed to this FIFO are
transmitted by a hardware handshake to the peripheral using the standard parallel port protocol.
Transfers to the FIFO are byte-aligned.
When the direction bit is 0, bytes written or DMAed to this FIFO are transmitted by a hardware
handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte-
aligned.
When the direction bit is 1, data bytes from the peripheral are read via automatic hardware handshake
from ECP into this FIFO. Reads or DMAs from the FIFO return bytes of ECP data to the system.
Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction. Data in
the tFIFO is not transmitted to the parallel port lines. However, data in the tFIFO may be displayed on
the parallel port data lines.
This register is a read-only register. When it is read, 10H is returned. This indicates that this is an 8-bit
implementation.
The bit definitions are as follows:
BIT
11.3.5
11.3.6
11.3.7
11.3.8
11.3.9
4
3
2
1
0
ackInEn (Interrupt Request Enable). When this bit is set to logical 1, it enables interrupt
requests from the parallel port to the CPU on the low-to-high transition on ACK#.
SelectIn. This bit is inverted and output to the SLIN# output.
0: The printer is not selected.
1: The printer is selected.
nInit. This bit is output to the INIT# output.
Autofd. This bit is inverted and output to the AFD# output.
Strobe. This bit is inverted and output to the STB# output.
CFIFO (Parallel Port Data FIFO) Mode = 010
ECPDFIFO (ECP Data FIFO) Mode = 011
TFIFO (Test FIFO Mode) Mode = 110
CNFGA (Configuration Register A) Mode = 111
CNFGB (Configuration Register B) Mode = 111
DESCRIPTION
-122-
Publication Release Date: March 24, 2008
W83627UHG
Revision 1.44

Related parts for W83627UHG