M69000 Asiliant Technologies, M69000 Datasheet - Page 318

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Choose (M, N) = (211, 30) for best accuracy.
Therefore M is less than 255 and VLD = 1, P = 4.
PCB Layout Considerations
Clock synthesizers, like most analog components, must be isolated from the noise that exists on a PCB
power plane. Care must be taken not to route any high frequency digital signals in close proximity to the
analog sections. Inside the graphics controller chip, the clocks are physically located in the lower left corner
of the chip surrounded by low frequency input and output pins. This helps to minimize both internally and
externally coupled noise.
The memory clock and video clock power pins on the graphics controller chip each require similar RC
filtering to isolate the synthesizers from the V
CVCCn/CGND pair is shown below:
The suggested method for layout assumes a multi-layer board including VCC and GND planes. All ground
connections should be made as close to the pin/component as possible. The CVCC trace should route from
the graphics controller through the pads of the filter components. The trace should NOT be connected to
the filter components by a stub. All components (particularly the nearest 0.1 F capacitor) should be placed
as close as possible to the graphics controller.
&+,36
69000 Databook
F
M/N = 0.879127
XRC0 = 211 - 2 = 209 (D1h)
XRC1= 30 - 2 = 28 (1Eh)
XRC3= 0010 0100 = 24h
REF
/(RDS x N) = 157.3KHz
V D D
0 .1 F
1 0
4 7 F
Subject to Change Without Notice
+
Clock Generation
CC
plane and from each other. The filter circuit for each
0 .1 F
D C K G N D /
D C K V C C /
M C K G N D
M C K V C C
Revision 1.3 8/31/98
B-5