M69000 Asiliant Technologies, M69000 Datasheet - Page 301

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

18-2
ER00
read/write at memory space offset 0x400100h
word or doubleword accessible
31
30
29-15
14
13-7
6
5-0
&+,36
Output
BBLT
Rsvd
Idle
En
(0)
(0)
31
Int
15
Output
Rsrvd
VBlnk
Dsply
BitBLT Engine Idle Interrupt Output Enable
Reserved
Reserved
Display Vertical Blanking Period Interrupt Output Enable
Reserved
Video Capture Vertical Sync Interrupt Output Enable
Reserved
(0)
En
(0)
30
14
Int
69000 Databook
Central Interrupt Control Register
29
13
0: No hardware interrupt is output to the host when the BitBLT engine becomes idle after
performing a BitBLT operation.
1: Causes a hardware interrupt to be output to the host when the BitBLT engine becomes
idle after performing a BitBLT operation.
This bit always returns a value of 0 when read.
These bits always return the value of 0 when read.
0: No hardware interrupt is output to the host when the last pixel of the last scan line within
the active display area is drawn on pipeline A.
1: Causes a hardware interrupt to be output to the host when the last pixel of the last scan
line within the active display area is drawn on pipeline A.
These bits always return the value of 0 when read.
0: No hardware interrupt is output to the host at the start of each vertical sync pulse from
the acquisition data source.
1: Causes a hardware interrupt to be output to the host at the start of each vertical sync
pulse from the acquisition data source.
These bits always return the value of 0 when read.
28
12
27
11
Memory-Mapped Wide Extension Registers
(00:0000:0)
Reserved
26
10
Subject to Change Without Notice
25
9
24
8
(00:0000:0000:0000)
23
Reserved
7
Output
VSync
V Cap
22
Int
En
(0)
6
21
5
20
4
19
Reserved
(00:0000)
3
Revision 1.3 8/31/98
18
2
17
1
16
0