M69000 Asiliant Technologies, M69000 Datasheet - Page 104

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

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Vertical Display Enable End Bit 8
The vertical display enable end is a 10-bit or 12-bit value that specifies the number of the last
scanline within the active display area.
In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the vertical
display enable end is specified with a 10-bit value. The 8 least significant bits of the vertical display
enable are supplied by bits 7-0 of the Vertical Display Enable End Register (CR12), and the most
and second-most significant bits are supplied by bit 6 and bit 1 of this register (CR07), respectively.
In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical display
enable end is specified with a 12-bit value. The 8 least significant bits of the vertical display enable
are supplied by bits 7-0 of the Vertical Display Enable End Register (CR12), and the 4 most
significant bits are supplied by bits 3-0 of the Extended Vertical Display End Enable Register
(CR31). In extended modes, neither bit 6 nor bit 1 of this register (CR07) are used.
This 10-bit or 12-bit value should be programmed to be equal to the number of the last scanline
within in the active display area. Since the active display area always starts on the 0th scanline,
this number should be equal to the total number of scanlines within the active display area minus 1.
Vertical Total Bit 8
The vertical total is a 10-bit or 12-bit value that specifies the total number of scanlines. This includes
the scanlines both inside and outside of the active display area.
In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the vertical total
is specified with a 10-bit value. The 8 least significant bits of the vertical total are supplied by bits
7-0 of the Vertical Total Register (CR06), and the most and second-most significant bits are
supplied by bit 5 and bit 0 of this register (CR07), respectively.
In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical total is
specified with a 12-bit value. The 8 least significant bits of the vertical total are supplied by bits 7-
0 of the Vertical Total Register (CR06), and the 4 most significant bits are supplied by 3-0 bits of
the Extended Vertical Total Register (CR30). In extended modes, neither bit 5 nor bit 0 of this
register (CR07) are used.
This 10-bit or 12-bit value should be programmed to be equal to the total number of scanlines minus
2.
69000 Databook
Subject to Change Without Notice
CRT Controller Registers
Revision 1.3 8/31/98
9-11