M69000 Asiliant Technologies, M69000 Datasheet - Page 102

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

5
4
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Vertical Total Bit 9
The vertical total is a 10-bit or 12-bit value that specifies the total number of scanlines. This includes
the scanlines both inside and outside of the active display area.
In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the vertical total
is specified with a 10-bit value. The 8 least significant bits of the vertical total are supplied by bits
7-0 of the Vertical Total Register (CR06), and the most and second-most significant bits are
supplied by bit 5 and bit 0 of this register (CR07), respectively.
In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical total is
specified with a 12-bit value. The 8 least significant bits of the vertical total are supplied by bits 7-
0 of the Vertical Total Register (CR06), and the 4 most significant bits are supplied by 3-0 bits of
the Extended Vertical Total Register (CR30). In extended modes, neither bit 5 nor bit 0 of this
register are used.
This 10-bit or 12-bit value should be programmed to be equal to the total number of scanlines minus
2.
Line Compare Bit 8
This bit provides the second most significant bit of a 10-bit value that specifies the scanline at which
the memory address counter restarts at the value of 0. Bit 6 of the Maximum Scanline Register
(CR09) supplies the most significant bit, and bits 7-0 of the Line Compare Register (CR18) supply
the 8 least significant bits.
Normally, this 10-bit value is set to specify a scanline after the last scanline of the active display
area. When this 10-bit value is set to specify a scanline within the active display area, it causes that
scanline and all subsequent scanlines in the active display area to display video data starting at the
very first byte of the frame buffer. The result is what appears to be a screen split into a top and
bottom part, with the image in the top part being repeated in the bottom part.
When used in cooperation with the Start Address High Register (CR0C) and the Start Address Low
Register (CR0D), it is possible to create a split display, as described earlier, but with the top and
bottom parts displaying different data. The top part will display whatever data exists in the frame
buffer starting at the address specified in the two start address registers (CR0C and CR0D), while
the bottom part will display whatever data exists in the frame buffer starting at the first byte of the
frame buffer.
69000 Databook
Subject to Change Without Notice
CRT Controller Registers
Revision 1.3 8/31/98
9-9