M69000 Asiliant Technologies, M69000 Datasheet - Page 275

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

16-20
MR28
read/write at I/O address 3D3h with index at address 3D2h set to 28h
7-0
MR2A
read/write at I/O address 3D3h with index at address 3D2h set to 2Ah
default = 00h
7-0
MR2B
read/write at I/O address 3D3h with index at address 3D2h set to 2Bh
default = 00h
7-3
2-0
&+,36
7
7
7
Playback Line Memory Fetch Width Bits 7-0
Playback Window X-LEFT Bits 7-0
Reserved
Playback Window X-LEFT Bits 10-8
69000 Databook
Playback Line Memory Fetch Width Register
Playback Window X-LEFT Low Register
Playback Window X-LEFT High Register
These 8 bits specify the number of quadwords read by the playback engine from the frame
buffer to display a horizontal line’s worth of video data. Normally, this value is set equal to
the actual number of quadwords required to store a horizontal line’s worth of video data
captured from the video data port -- i.e., normally this value is the same as that of register
MR0C.
If bit 6 of the Playback Control 3 Register (MR0C) is set to 0 then this register also specifies
the number of quadwords out of a horizontal line’s worth of video data that is actually played
back, starting at the left-most edge of the video playback window.
This value is calculated as follows:
6
6
6
Reserved
( (width of line in pixels) / (number of pixels per quadwords) ) - 1.
5
5
5
Playback Line Memory Fetch Width Bits 7-0
Subject to Change Without Notice
Playback Window X-LEFT Bits 7-0
Multimedia Registers
4
4
4
3
3
3
Playback Window X-LEFT Bits 10-8
2
2
2
Revision 1.3 8/31/98
1
1
1
0
0
0