M69000 Asiliant Technologies, M69000 Datasheet - Page 237

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

15-22
FR1A
read/write at I/O address 3D1h with index at I/O address 3D0h set to 1Ah
7-2
1
0
FR1E
read/write at I/O address 3D1h with index at I/O address 3D0h set to 1Eh
7
6-0
&+,36
ACDCLK
Control
7
7
Reserved (Writable)
These bits should always be set to the value of 0.
STN-DD Frame Acceleration Enable
Enabling STN-DD frame acceleration doubles the screen refresh rate on an attached STN-DD
panel relative to an attached CRT (each CRT frame corresponds to two STN-DD panel frames).
The required memory bandwidth does not increase. In the simultaneous display mode, if the CRT
refresh rate is 60Hz, the STN-DD panel refresh rate is 120Hz when STN-DD frame acceleration is
enabled. Under the same conditions, the STN-DD panel refresh rate is 60Hz when STN-DD frame
acceleration is disabled. Usually, STN-DD panels display higher quality images when STN-DD
frame acceleration is enabled. If STN-DD frame acceleration is disabled, then the STN-DD buffer
must be large enough to hold an entire frame consisting of 3-bits per pixel organized as 10 pixels
per 32-bit Dword. With STN-DD frame acceleration enabled, the required STN-DD buffer size is
half this amount (only half a frame need be stored).
STN-DD Buffering Enable
0: Disables STN-DD buffering. This is the default after reset.
1: Enables STN-DD buffering.
STN-DD buffering is required for STN-DD panel operation. For STN-SS panel operation, STN-DD
buffering is not required so this bit must be set to 0.
M (ACDCLK) Control
M (ACDCLK) Count (ACDCNT)
69000 Databook
M (ACDCLK) Control Register
STN-DD Buffering Control Register
0: The M (ACDCLK) phase changes depending on bits 0-6 of this register
1: The M (ACDCLK) phase changes every frame if the frame accelerator is not used. If
the frame accelerator is used, the M (ACDCLK) phase changes every other frame.
This register is used only in flat panel mode.
These bits define the number of HSyncs between adjacent phase changes on the M
(ACDCLK) output. These bits are effective only when bit 7 = 0 and the contents of this
register are greater than 2.
6
6
Reserved (Writable)
5
5
(0000:00)
Subject to Change Without Notice
Programmed Value = Actual Value - 2
Flat Panel Registers
4
4
M(ACDCLK) Count (ACDCNT)
3
3
2
2
Frame Accel
Enable
(0)
Revision 1.3 8/31/98
1
1
Buffering
Enable
(0)
0
0