M69000 Asiliant Technologies, M69000 Datasheet - Page 114

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

CR11
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 11h
7
Note:
6
5
Note:
4
Note:
3-0
&+,36
Protect Regs
0-7
7
Protect Registers 0-7
0: Enable writes to registers CR00-CR07.
1: Disable writes to registers CR00-CR07.
The ability to write to bit 4 of the Overflow Register (CR07) is not affected by this bit. Bit 4 of the
Overflow Register is always writable.
Reserved
Writes to this bit are ignored. In the VGA standard, this bit was used to switch between 3 and 5
frame buffer refresh cycles during the time required to draw each horizontal line.
Vertical Interrupt Enable
0: Enable the generation of an interrupt at the beginning of each vertical retrace period.
1: Disable the generation of an interrupt at the beginning of each vertical retrace period.
The hardware does not actually provide an interrupt signal which would be connected to an input
of the system’s interrupt controller. Bit 7 of Input Status Register 0 (ST00) indicates the status of
the vertical retrace interrupt, and can be polled by software to determine if a vertical retrace interrupt
has taken place. Bit 4 of this register can be used to clear a pending vertical retrace interrupt.
Vertical Interrupt Clear
Setting this bit to 0 clears a pending vertical retrace interrupt. This bit must be set back to 1 to
enable the generation of another vertical retrace interrupt.
The hardware does not actually provide an interrupt signal which would be connected to an input
of the system’s interrupt controller. Bit 7 of Input Status Register 0 (ST00) indicates the status of
the vertical retrace interrupt, and can be polled by software to determine if a vertical retrace interrupt
has taken place. Bit 5 of this register can be used to enable or disable the generation of vertical
retrace interrupts.
Vertical Sync End
These 4 bits provide a 4-bit value that specifies the end of the vertical sync pulse relative to its
beginning.
This 4-bit value should be set to the least significant 4 bits of the result of adding the length of the
vertical sync pulse in terms of the number of scanlines that occur within the length of the vertical
sync pulse to the value that specifies the beginning of the vertical sync pulse. See the description
of the Vertical Sync Start Register (CR10) for more details.
69000 Databook
Vertical Sync End Register
Reserved
6
Vert Int
Enable
5
Subject to Change Without Notice
CRT Controller Registers
Vert Int Clear
4
3
Vertical Sync End
2
Revision 1.3 8/31/98
1
0
9-21