M69000 Asiliant Technologies, M69000 Datasheet - Page 227

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

15-12
FR10
read/write at I/O address 3D1h with index at I/O address 3D0h set to 10h
7
6-4
.
&+,36
Reserved
[6-4]
[6-4]
(R/W)
Bits
[6-4]
Bits
Bits
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
4-bit pack color STN-DD w/frame accel.
Monochrome STN-DD w/o frame accel.
(0)
7
Reserved (R/W) (reset state: 0)
Shift Clock Divide (reset state: 000)
These bits specify the frequency ratio between the internal dot clock (DCLK) and flat panel shift
clock (SHFCLK) signal.
69000 Databook
SHFCLK
SHFCLK
SHFCLK
FP Format 0 Register
DCLK/2
DCLK/2
DCLK/4
DCLK/8
DCLK/2
DCLK
DCLK
DCLK
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Color TFT
6
Shift Clock Divide
SHFCLK
SHFCLK
SHFCLK
Pixel /
Pixel /
Pixel /
2 2/3
5 1/3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
2
1
2
4
8
(000)
5
Subject to Change Without Notice
Max bpp
Max bpp
Max bpp
24
12
16
16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
4
8
8
Flat Panel Registers
4
3
Mono / Color
[6-4]
[6-4]
Bits
Bits
Bits
[6-4]
4-bit pack color STN-DD w/o frame accel.
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
Monochrome STN-DD w/o frame accel.
(00)
4-bit pack Color STN-SS
SHFCLK
SHFCLK
DCLK/16
SHFCLK
2
DCLK/2
DCLK/4
DCLK/2
DCLK/4
DCLK/8
DCLK/2
DCLK/4
DCLK
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SHFCLK
SHFCLK
SHFCLK
Pixel /
Pixel /
Pixel /
Revision 1.3 8/31/98
1
2 2/3
5 1/3
2 2/3
5 1/3
1 1/3
—
—
—
—
—
16
—
—
—
—
—
—
—
—
—
—
2
4
8
Panel Type
(00)
Max bpp
Max bpp
Max bpp
0
16
—
—
—
—
—
16
—
—
—
16
—
—
—
—
—
—
—
4
8
2
4
8
8