M69000 Asiliant Technologies, M69000 Datasheet - Page 232

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

3
2
1
0
&+,36
FP Display Enable (FP Blank#) Select
0: The FP Display Enable is inactive during vertical blank time because the output comes from
inverting both the FP Vertical and Horizontal blank. FP HSync is not generated during vertical blank
except when bit 4 is set to 1. In 480-line DD panels, this option will generate exactly 240 FP HSync
(LP) pulses. This is the default after reset.
1: The FP Display Enable is active during Vertical blank time since the output comes from inverting
the FP Horizontal Blank enable. FP HSync will also be active during vertical blank.
This bit controls FP Display Enable (FP Blank#) generation. This bit also affects FP HSync (LP)
generation.
Shift Clock Mask for STN-DD
0: Allow Shift Clock output to toggle in first line of Vertical Blank. This is the default after reset.
1: Force Shift Clock output low in first line of Vertical Blank.
This is an option to eliminate dark lines in the middle of STN-DD panels.
Shift Clock Mask
0: Allow Shift Clock output to toggle outside the display enable interval. This is the default after
reset.
1: Force Shift Clock output low outside the display enable interval.
Shift Clock Divide
0: Shift Clock to Dot Clock relationship is specified by FR10 bits 6-4. This is the default after reset.
1: Shift Clock is further divided by 2 and different video data is valid on the rising and falling edges
of Shift Clock.
69000 Databook
Subject to Change Without Notice
Flat Panel Registers
Revision 1.3 8/31/98
15-17