M69000 Asiliant Technologies, M69000 Datasheet - Page 22

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

1-2
Flicker reduction can be accomplished by averaging the contents of successive horizontal and vertical lines.
See Figure 1-1. The flicker reduction circuit is in pixel data path, with the vertical averaging circuit followed
by the horizontal averaging circuit. Both have bypass controls (Vertical filter enable and Horizontal filter
enable). This flicker averaging circuit is placed before the DAC and before the flat panel pick off. The flat
panel pins can be used for test verification of correct filter operation.
For the non-flicker reduction mode, the display line data is stored sequentially in the FIFO buffer. For the
flicker reduction mode the FIFO buffer data is written in strips of segments because the vertical filter
averages the current and next line pixels. Each segment is written to alternate locations in the FIFO buffer.
See Fig. 1-2.
The write pointer is modified to skip through the FIFO buffer. A current/next line flag is carried through the
display pipeline to keep track of which line the pixel comes from. This is needed for the color key logic and
the vertical filter averaging circuitry to align to the correct segment of pixels. The MMUX color key is formed
on the “current” pixel pair.
Flicker reduced NTSC is supported in the following extended graphics modes:
&+,36
69000 Databook
NTSC:
PAL:
Color Depths:
NO RM AL
640x480, 60 Hz Interlaced
8 bit indexed
800x600, 50 Hz, Interlaced
15 bit RGB
16 bit RGB
24 bit RGB
Figure 1-1: Pixel Averaging Circuit
Subject to Change Without Notice
HO RIZ ON T AL A V E R A G IN G
VE RT ICA L A V E RA GING
Introduction / Overview
FIG . 1
VE RT ICA L A N D H O R IZ O NT A L
AV ER AG IN G
Revision 1.3 8/31/98
F U L L B L AC K
3 /4 B LA C K
1 /2 B LA C K
1 /4 B LA C K
1 /8 B LA C K
W H ITE