M69000 Asiliant Technologies, M69000 Datasheet - Page 226

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

FR0F
read/write at I/O address 3D1h with index at I/O address 3D0h set to 0Fh
Note:
from a value programmed into this register (see bits 0-4 below) and is reset back to that count by read or
write accesses to graphics memory or standard VGA I/O. Reading or writing extended VGA registers does
not reset the counter. If no accesses occur, the counter increments until the end of its programmed interval
then activates either the ENABKL pin or Panel Off mode (as selected by bit-6 below). The timer count does
not need to be reloaded once programmed and the timer enabled. Any access to the chip with the timer
timed out (ENABKL active or Panel Off mode active) resets the timer and deactivates the ENABKL (or Panel
Off mode) pin. The activity timer uses the same clock as the power sequencing logic. The delay intervals
assume a 37.5 KHz clock. If using a 32KHz input, scale the delay intervals accordingly.
7
6
5
4-0
&+,36
Activity
Timer
7
This register controls the activity timer functions. The activity timer is an internal counter that starts
Enable Activity Timer
0: Disable activity timer (default on reset)
1: Enable activity timer
Activity Timer Action
0: When the activity timer count is reached, the ENABKL pin is activated (driven low to turn the
backlight off)
1: When the activity timer count is reached, Panel Off mode is entered.
Reserved (R/W)
Activity Timer Count
For a 37.5KHz power sequencing clock, the counter resolution is 28.1 seconds. The minimum
programmed value of 0 results in 28.1 seconds delay, and the maximum value of 1Eh results in a
delay of 15 minutes.
69000 Databook
Activity Timer Control Register
Timer Action
6
Reserved
(R/W)
5
Subject to Change Without Notice
Flat Panel Registers
4
3
Activity Timer Count
2
Revision 1.3 8/31/98
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