M69000 Asiliant Technologies, M69000 Datasheet - Page 137

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

10-2
SRX
read/write at I/O address 3C4h
This register is cleared to 00h by reset.
7-3
2-0
Note:
Note:
SR00
read/write at I/O address 3C5h with index at address 3C4h set to 00h
7-2
1
0
&+,36
7
7
Reserved
Sequencer Register Index
These three bits are used to select any one of the sequencer registers, SR00 through SR07, to be
accessed via the data port at I/O location 3C5.
SR02 is referred to in the VGA standard as the Map Mask Register. However, the word “map” is
used with multiple meanings in the VGA standard and was therefore deemed too confusing, hence
the reason for calling it the Plane Mask Register.
SR07 is a standard VGA register that was not documented by IBM.
It is not a CHIPS extension.
Reserved
Synchronous Reset
Setting this bit to 0 commands the sequencer to perform a synchronous clear and then halt. The
sequencer should be reset via this bit before changing the Clocking Mode Register (SR01) if the
memory contents are to be preserved. However, leaving this bit set to 0 for longer than a few tenths
of a microsecond can still cause data loss in the frame buffer. No register settings are changed by
performing this type of reset.
0: Forces synchronous reset and halt
1: Permits normal operation
Asynchronous Reset
Setting this bit to 0 commands the sequencer to perform a clear and then halt. Resetting the
sequencer via this bit can cause data loss in the frame buffer. No register settings are changed by
performing this type of reset.
0: Forces asynchronous reset
1: Permits normal operation
69000 Databook
Sequencer Index Register
Reset Register
6
6
Reserved
5
5
Reserved
Subject to Change Without Notice
Sequencer Registers
4
4
3
3
2
2
Sequencer Register Index
Sync Reset
Revision 1.3 8/31/98
1
1
Async Reset
0
0