M69000 Asiliant Technologies, M69000 Datasheet - Page 156

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M69000

Manufacturer Part Number
M69000
Description
Manufacturer
Asiliant Technologies
Datasheet

Specifications of M69000

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AR10
read at I/O address 3C1h, write at I/O address 3C0h with index at address 3C0h set to 10h
7
6
Note: This bit is set to 0 for all of the standard VGA modes, except mode 13h.
5
Note:
4
3
Note:
&+,36
Palette Bits
P5, P4
Select
7
Palette Bits P5, P4 Select
Pixel Width/Clock Select
Pixel Panning Compatibility
This bit has application only when split-screen mode is being used, where the display area is
divided into distinct upper and lower regions which function somewhat like separate displays.
Reserved
Enable Blinking/Select Background Intensity
The blinking rate is derived by dividing the VSYNC signal. The Blink Rate Control Register (FR19)
defines the blinking rate.
69000 Databook
Mode Control Register
Pixel Width/
Clk Select
0: P5 and P4 for each of the 16 selected colors (for modes that use 16 colors) are
individually provided by bits 5 and 4 of their corresponding Palette Registers (AR00-0F).
1: P5 and P4 for all 16 of the selected colors (for modes that use 16 colors) are provided
by bits 1 and 0 of Color Select Register (AR14).
0: Six bits of video data (translated from 4 bits via the palette) are output every dot clock.
1: Two sets of 4 bits of data are assembled to generate 8 bits of video data which is output
every other dot clock, and the Palette Registers (AR00-0F) are bypassed.
0: Scroll both the upper and lower screen regions horizontally as specified in the Horizontal
Pixel Panning Register (AR13).
1: Scroll only the upper screen region horizontally as specified in the Horizontal Pixel
Panning Register (AR13).
0: Disables blinking in graphics modes and, in text modes, sets bit 7 of the character
attribute bytes to control background intensity, instead of blinking.
1: Enables blinking in graphics modes and, in text modes, sets bit 7 of the character
attribute bytes to control blinking, instead of background intensity.
6
Panning
Compat
Pixel
5
Subject to Change Without Notice
Attribute Controller Registers
Reserved
4
Select Bkgnd
En Blink/
Int
3
En Line Gr
Char Code
2
Display Type
Select
Revision 1.3 8/31/98
1
Alpha Mode
Graphics/
0
12-3

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