ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 95

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 9-3:
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7-0
PKTCNT7
R-0
INT
R-0
INT: Interrupt Pending Status bit
1 = One of the EIR bits is set and enabled by the EIE register. If INTIE (EIE<15>) is set, the INT pin is
0 = No enabled interrupts are currently pending. The INT pin is being driven high.
FCIDLE: Flow Control Idle Status bit
1 = Internal flow control state machine is Idle. It is safe to change the FCOP (ECON1<7:6>) and
0 = Internal flow control state machine is busy. Do not modify the FCOP (ECON1<7:6>) or FULDPX
RXBUSY: Receive Logic Active Status bit
1 = Receive logic is currently receiving a packet. This packet may be discarded in the future if an RX
0 = Receive logic is Idle
CLKRDY: Clock Ready Status bit
1 = Normal operation
0 = Internal Ethernet clocks are not running and stable yet. Only the ESTAT and EUDAST registers
Reserved: Ignore on read
PHYDPX: PHY Full Duplex Status bit
1 = PHY is operating in Full-Duplex mode
0 = PHY is operating in Half-Duplex mode
Reserved: Ignore on read
PHYLNK: PHY Linked Status bit
1 = Ethernet link has been established with a remote Ethernet partner
0 = No Ethernet link present
PKTCNT<7:0>: Receive Packet Count bits
Number of complete packets that are saved in the RX buffer and ready for software processing. Set the
PKTDEC (ECON1<8>) bit to decrement this field.
PKTCNT6
FCIDLE
also driven low.
FULDPX (MACON2<0>) bits.
(MACON2<0>) bits.
buffer overflow occurs or a receive filter rejects it, so this bit does not necessarily indicate that an
RX packet pending interrupt will occur.
should be accessed.
R-0
R-0
ESTAT: ETHERNET STATUS REGISTER
W = Writable bit
‘1’ = Bit is set
PKTCNT5
RXBUSY
R-0
R-0
PKTCNT4
CLKRDY
R-0
R-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PKTCNT3
ENC424J600/624J600
R-0
R-0
r
PKTCNT2
PHYDPX
R-0
R-0
x = Bit is unknown
PKTCNT1
R-0
R-0
r
DS39935C-page 93
PKTCNT0
PHYLNK
R-0
R-0
bit 8
bit 0