ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 117

IC ETHERNET CTRLR W/SPI 64-TQFP

ENC624J600-I/PT

Manufacturer Part Number
ENC624J600-I/PT
Description
IC ETHERNET CTRLR W/SPI 64-TQFP
Manufacturer
Microchip Technology
Datasheets

Specifications of ENC624J600-I/PT

Package / Case
64-TFQFP
Controller Type
Ethernet Controller
Interface
SPI
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
96mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Input Voltage Range (max)
5.5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3 V to 3.6 V
Supply Current (max)
117 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ENC624J600-I/PT
Manufacturer:
Microchip
Quantity:
3 200
Part Number:
ENC624J600-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Company:
Part Number:
ENC624J600-I/PT
Quantity:
4 900
Company:
Part Number:
ENC624J600-I/PT
Quantity:
12 888
REGISTER 12-7:
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-5
bit 4
bit 3-2
bit 1
bit 0
R-0
R-0
r
r
Reserved: Ignore on read
PDFLT: Parallel Detection Fault Status bit
1 = Parallel detection did not detect a valid link partner; automatically cleared when register is read
0 = Parallel detection is still in progress or a valid link partner is connected
Reserved: Ignore on read
LPARCD: Link Partner Abilities Received Status bit
1 = PHANLPA register has been written with a new value from the link partner; automatically cleared
0 = PHANLPA contents have not changed since the last read of PHANE
LPANABL: Link Partner Auto-Negotiation Able Status bit
1 = Link partner implements auto-negotiation
0 = Link partner does not implement auto-negotiation
when register is read
R-0
R-0
r
r
PHANE: PHY AUTO-NEGOTIATION EXPANSION REGISTER
LH = Latch High bit
W = Writable bit
‘1’ = Bit is set
R-0
R-0
r
r
R/LH-0
PDFLT
R-0
r
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ENC424J600/624J600
R-0
R-0
r
r
R-0
R-0
r
r
x = Bit is unknown
LPARCD
R/LH-0
R-0
r
DS39935C-page 115
LPANABL
R-0
R-0
r
bit 8
bit 0

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