ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 54

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC424J600/624J600
5.2
Unlike the serial interface, the PSP interface does not
use opcodes or a command architecture to control the
device. Instead, the memory space is accessed directly
using
Section 3.1.2 “PSP Interface Maps”. Control SFRs
are read and written to directly, or manipulated through
their accompanying Bit Set and Bit Clear registers.
In 16-bit modes, each address (from 0 to 16,384) points
to a different word. The individual write high and write
low strobes allow the upper or lower byte of each word
to be written individually.
5.2.1
Direct addressing allows the host controller to access
all SFRs and SRAM buffer addresses in the
ENCX24J600 memory space directly. This provides the
greatest flexibility and speed for accessing the SRAM
buffer. However, this configuration requires up to
15 address pins to be driven by the host controller. This
may
applications.
In Modes 1 through 6, it is possible to conserve six
address pins by tying them to V
only the addresses corresponding to the SFR area of
the memory space can be directly addressed. The
SRAM buffer memory can still be accessed, but only
through the EGPDATA, ERXDATA and EUDADATA
data windows in the SFR space, described in
Section 3.5.5 “Indirect SRAM Buffer Access”.
Indirect buffer access works well for Multiplexed
modes, such as PSP Modes 5, 6, 9 and 10. In these
modes, the auto-incrementing feature of the Data
Window Pointers allows access to the buffer at speeds
similar to byte-wise demultiplexed access, since a
separate address phase in not required for each byte.
The 8-Bit PSP modes have separate addresses for the
low and high bytes of each register. Since these
modes, therefore, have a “longer” memory space (i.e.,
more individual addresses), indirect access requires
9 lines to address all registers between 7E00h and
7FFFh. In contrast, the 16-bit modes require only
8 lines to address all of the registers in their SFR range
(3F00h to 3FFFh). Even so, using indirect access still
saves six pins in either data width: AD<14:9> in 8-bit
modes and AD<13:8> in 16-bit modes.
5.2.2
In Multiplexed Address/Data modes (PSP Modes 5
through 10), the ENCX24J600 implements an internal
address latch. This allows a reduction in the total number
of interface pins by multiplexing the data and addresses
that need to be communicated onto a single bus.
DS39935C-page 52
be
the
Using the PSP Interface
prohibitive
DIRECT AND INDIRECT SRAM
BUFFER ACCESS
ADDRESS LATCHING
addressing
in
schemes
smaller,
DD
. In this configuration,
pin-constrained
described
in
If only one write select pin is available on the host con-
maximum ESD performance, it is recommended that
In 8-bit modes, the address latch is implemented on all
of the AD pins. In 16-bit modes, the address latch is
implemented for only the AD<13:0> pins. Because it
spans all required address lines, it is necessary to
present the desired address to the ENCX24J600 for
only a brief period while strobing the Address Latch
(AL) pin. On 8-bit interfaces, where AD<14:8> are used
exclusively for addressing, it is not necessary to drive
these upper address lines with a valid address
continually through read and write operations.
During operation, strobing the AL pin high and then low
causes the address presented on the AD pins to be
saved to the address latch. The address is retained for
all future read and write operations. It is retained until
either a POR event occurs or a subsequent write to the
address latch occurs by restrobing AL. This allows
multiple read and write requests to take place to the
same address, without requiring multiple address
latching operations.
The address latch does not auto-increment after
accesses. However, by using the indirect buffer access
method, it is possible to sequentially read or write an
entire array of sequential SRAM locations without
updating the address latch.
5.2.3
The 16-Bit PSP modes make use of either two write
pins (WRL and WRH), or a R/W select and two Byte
Lane (B0SEL and B1SEL) controls. When writing to the
device, these pins allow the host controller to instruct
whether to write only the low byte, only the high byte or
both bytes.
troller, the high and low selection pins may be tied
together to create a single 16-bit write strobe. When this
is done, only word writes are possible. However, the host
controller can still write single bytes when accessing the
SRAM buffer through the EGPDATA, ERXDATA or
EUDADATA Window registers, which always perform
8-bit accesses.
5.2.4
Any unused PSP pins are placed in a high-impedance
state, regardless of the state of the CS pin. For
unused interface pins not be allowed to float. Instead, it
is recommended that unused interface pins be tied to
either V
SS
or V
WRITE SELECT PINS
UNUSED INTERFACE PINS
DD
.
 2010 Microchip Technology Inc.