ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 139

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.0
Due to the high bandwidth and long cable length require-
ments, Ethernet applications can utilize a significant
amount of power. ENC424J600/624J600 devices
include power-down and PHY power management
features to assist low-power applications. While features
cannot completely mitigate power requirements, they
can help reduce power consumption when the Ethernet
interface is not needed.
16.1
The ENCX24J600 may be placed in Power-Down
mode through the command interface. In this mode, the
device will no longer be able to transmit or receive any
packets or perform DMA operations. However, most
registers, and all buffer memories, retain their states
and remain accessible by the host controller. The clock
driver also remains operational, leaving the CLKOUT
function unaffected. However, the MAC/MII and PHY
registers all become inaccessible, and the PHY
registers lose their current states.
To power-down the Ethernet interface:
1.
2.
3.
4.
5.
6.
To resume normal operation, the PHY registers need to
be reconfigured after wake-up. The typical restart
sequence is:
1.
2.
3.
 2010 Microchip Technology Inc.
Turn off the Modular Exponentiation and AES
engines by clearing CRYPTEN (EIR<15>).
Turn off packet reception by clearing RXEN
(ECON1<0>).
Wait for any in-progress receptions to complete
by polling RXBUSY (ESTAT<13>) until it is clear.
Wait for any current transmission operation to
complete by verifying that TXRTS (ECON1<1>)
is clear.
Power-down the PHY by setting the PSLEEP bit
(PHCON1<11>).
Power-down the Ethernet interface by clearing
ETHEN and STRCH (ECON2<15,14>). Dis-
abling the LED stretching behavior is necessary
to ensure no LEDs get trapped in a perpetually
illuminated state in the event they are being
stretched on when ETHEN is cleared.
Wake-up the Ethernet interface by setting
ETHEN and STRCH (ECON2<15,14>).
Wake-up the PHY by clearing PSLEEP
(PHCON1<11>). Care should be taken to modify
only the PSLEEP bit.
Restore receive capabilities by setting RXEN
(ECON1<0>).
POWER-SAVING FEATURES
General Power-Down
ENC424J600/624J600
After leaving Sleep mode, there will be a delay of
several hundred milliseconds before a new link is
established. If the host controller attempts to transmit
any Ethernet packets before the link is established, the
PHY will suppress the transmission onto the wire to
avoid interfering with auto-negotiation or violating
IEEE 802.3 standards. The link status can be moni-
tored through the Link Change Interrupt Flag, LINKIF
(EIR<11>), and PHYLNK status bit (ESTAT<8>).
16.2
ENC424J600/624J600 devices also support an Energy
Detect Power-Down mode. In this mode, the PHY
remains powered down until a signal is detected on the
Ethernet interface. While no packets can be sent or
received, the internal PHY configuration is maintained.
This is useful for applications in which the Ethernet
cable may not always be connected, but need to
automatically activate when a network cable is
attached by the user and a link partner is detected.
When a signal is detected on the Ethernet medium, the
EDSTAT flag (PHCON2<1>) is set.
To enable Energy Detect Power-Down mode, set the
EDPWRDN bit (PHCON2<13>). The PHY auto-
matically powers up and down based on the value of
EDSTAT. When in Energy Detect Power-Down, the
host microcontroller should monitor the Ethernet link
status via the LINKIF interrupt flag and PHYLNK status
bit. When linked, it should set ETHEN and STRCH
(ECON2<15,14>) and begin using the network inter-
face as normal. When unlinked, it should clear ETHEN
and STRCH to save power. To resume normal opera-
tion, clear EDPWRDN. While the PHY is in Energy
Detect Power-Down mode, the transmit logic will
indefinitely hold off transmissions when unlinked.
Therefore, if the application attempts to transmit a
packet by setting TXRTS (ECON1<1>), this bit may not
clear itself or cause a transmit interrupt to occur until
the user plugs the device into another link partner.
Energy Detect Power-Down
DS39935C-page 137