ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet
ENC624J600-I/PT
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ENC624J600-I/PT Summary of contents
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... Stand-Alone 10/100 Ethernet Controller 2010 Microchip Technology Inc. ENC424J600/624J600 Data Sheet with SPI or Parallel Interface DS39935C ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... SRAM Pin Speed Device (bytes) Count (Mbps) ENC424J600 24K 44 10/100 ENC624J600 24K 64 10/100 2010 Microchip Technology Inc. ENC424J600/624J600 • Security Engines: - High-performance, modular exponentiation engine with up to 1024-bit operands - Supports RSA exchange algorithms - High-performance AES encrypt/decrypt ...
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... ENC424J600/624J600 Pin Diagrams 44-Pin TQFP and QFN CS/CS SO/WR/EN SI/RD/RW SCK/AL AD0 AD1 AD2 AD3 CAP V DD DS39935C-page ENC424J600 SSTX TPOUT- TPOUT+ V SSTX V DDTX TPIN- TPIN+ V DDRX V SSRX V SSPLL V DDPLL 2010 Microchip Technology Inc. ...
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... Pin Diagrams (Continued) 64-Pin TQFP CS/CS SO/WR/WRL/EN/B0SEL SI/RD/RW SCK/AL/PSPCFG4 AD0 AD1 AD2 AD3 CAP V DD 2010 Microchip Technology Inc. ENC424J600/624J600 ENC624J600 SSTX 31 TPOUT- 30 TPOUT SSTX 28 V DDTX TPIN TPIN DDRX 24 V SSRX V 23 SSPLL 22 V DDPLL A11 19 A10 18 PSPCFG3 17 PSPCFG2 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39935C-page 4 2010 Microchip Technology Inc. ...
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... Communication protocols, such as TCP, can use this memory for saving data which may need to be retransmitted. For easy ENC624J600 family device is preprogrammed with a unique nonvolatile MAC address. In most cases, this many optional allows the end device to avoid a serialized programming step. ...
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... DMA and m1 Checksum Crypto Cores TX Control m2 Logic Flow Control Memory Host Interface SRAM 24 Kbytes Power-on PLL Reset Regulator CLKOUT MAC PHY TPOUT+ TX MII Interface TPOUT- TPIN+ RX TPIN- MIIM Interface RBIAS OSC1 25 MHz Oscillator OSC2 Voltage V CAP 2010 Microchip Technology Inc. ...
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... INT 24 34 LEDA 10 15 LEDB 9 14 Legend Input Output Power; CMOS = CMOS compatible input buffer; ANA = Analog level input/output 2010 Microchip Technology Inc. ENC424J600/624J600 Input Buffer I/O CMOS PSP Multiplexed Address Input and/or Bidirectional Data Bus I/O CMOS I/O CMOS ...
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... Ground Reference for 25 MHz Oscillator P — Ground Reference for PHY PLL Circuitry P — Ground Reference for PHY RX Circuitry P — Ground Reference for PHY TX Circuitry I CMOS PSP Write Strobe I CMOS PSP Write High Strobe I CMOS PSP Write Low Strobe Description 2010 Microchip Technology Inc. ...
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... The feedback resistor typically 1.5 M F approx. 3: The load capacitors’ value should be derived from the capacitive loading specification provided by the crystal manufacture. 2010 Microchip Technology Inc. ENC424J600/624J600 FIGURE 2-2: designed to 3.3V Clock from External System Open Note 1: Duty cycle restrictions must be observed ...
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... It is recommended that the resistor and DDRX be a surface mount type. FIGURE 2-4: ENCX24J600 . CAP V CONNECTIONS CAP ENCX24J600 +3. I/O, PHY Regulator +1.8V V CAP Core, RAM, MAC V SS RBIAS RESISTOR PHY RBIAS 12.4k1% 2010 Microchip Technology Inc. ...
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... TPOUT + TPIN 49.9, 1% 49.9 TPIN 2010 Microchip Technology Inc. ENC424J600/624J600 baseline wander correction (applicable to 100Base-TX) and automatic RX polarity correction (applicable to 10Base-T). Four 49.9Ω, 1% resistors are required for proper termination of the TX and RX transmission lines. If the board layout necessitates long traces between the ...
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... TX/RX events are occurring and the speed/duplex respectively, then the LEDB pin will be driven high while LEDA will be driven low. SINGLE COLOR LED CONNECTION 180 LED BI-COLOR LED CONNECTION 180 Bi-Color LED state is 100 Mbps/full duplex, 2010 Microchip Technology Inc. ...
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... SCK SDO SDI SPI Selected (internal weak pull- enabled) 2010 Microchip Technology Inc. ENC424J600/624J600 approximately s after power is applied to the device and the device exits Power-on Reset. If SPISEL is latched at a logic high state, the serial interface is enabled. If SPISEL is latched at a logic low state, the PSP interface is enabled ...
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... PSP pins be tied to either V However, these pins may be left floating desirable for board level layout and routing reasons. When using an ENC624J600 device in SPI mode recommended that the PSPCFG2 and PSPCFG3 pins be tied to either V or any logic high voltage, and not SS be left floating ...
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... When using the PSP interface, eight, or all sixteen of the ADx pins, may need level translation when perform- ing read operations on the ENCX24J600. The 8-bit 74ACT245 or 16-bit 74ACT16245 bus transceiver, or similar devices, may be useful in these situations. 2010 Microchip Technology Inc. ENC424J600/624J600 FIGURE 2-10: MCU INTx ...
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... ENC424J600/624J600 NOTES: DS39935C-page 16 2010 Microchip Technology Inc. ...
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... Bank 3 Unbanked (inaccessible using banked opcodes) PHY Register Area 16-Bit, MIIM Access Only 2010 Microchip Technology Inc. ENC424J600/624J600 3.1.1 SPI INTERFACE MAP When the SPI interface is selected, the device memory map is comprised of three memory address spaces (Figure ): • the SFR area • ...
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... Cryptographic Data (DMA access only) Unimplemented Special Function Registers (R/W) SFR Bit Set Registers SFR Bit Clear Registers PHY Register Area 00h 16-Bit, MIIM Access Only 1Fh 2010 Microchip Technology Inc. , still allows direct address DD (1) 0000h 0000h 5FFFh 2FFFh (2) 7800h ...
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... Non-sequential writes, such as writing to the low byte of one MAC register, the low byte of a second MAC register and then the high byte of the first register cannot be performed. 2010 Microchip Technology Inc. ENC424J600/624J600 3.2.3 SPI REGISTER MAP As previously described, the SFR memory is partitioned into four banks plus a special region that is not bank addressable ...
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... ECON2L 8E EUDARDPTL 6F ECON2H 8F EUDARDPTH 70 ERXWML 90 EUDAWRPTL 71 ERXWMH 91 EUDAWRPTH 72 EIEL 92 Reserved 73 EIEH 93 Reserved 74 EIDLEDL 94 Reserved 75 EIDLEDH 95 Reserved 76 EUDASTL 96 Reserved 77 EUDASTH 97 Reserved 78 EUDANDL 98 Reserved 79 EUDANDH 99 Reserved 7A ESTATL 9A Reserved 7B ESTATH 9B Reserved 7C EIRL 9C Reserved 7D EIRH 9D Reserved 7E ECON1L 9E — 7F ECON1H 9F — 2010 Microchip Technology Inc. (2) ...
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... EIRH 7E1E ECON1L 7E3E ECON1L 7E1F ECON1H 7E3F ECON1H 2010 Microchip Technology Inc. ENC424J600/624J600 The SFR maps for the 8-bit and 16-bit PSP interfaces are shown in Table 3-2 and Table 3-3, respectively. Addr Name Addr Name 7E40 MACON1L 7E60 ...
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... MIRD 3F44 EGPWRPT MISTAT 3F45 ERXRDPT EPAUS 3F46 ERXWRPT ECON2 3F47 EUDARDPT ERXWM 3F48 EUDAWRPT EIE 3F49 Reserved EIDLED 3F4A Reserved EUDAST 3F4B Reserved EUDAND 3F4C Reserved ESTAT 3F4D Reserved EIR 3F4E Reserved ECON1 3F4F — 2010 Microchip Technology Inc. ...
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... EIRSETH 7F3D 7F1E ECON1SETL 7F3E 7F1F ECON1SETH 7F3F Note 1: Bit Set and Bit Clear registers are not implemented for the base SFRs located between 7E80h and 7E9Fh. 2010 Microchip Technology Inc. ENC424J600/624J600 Name Addr Name EHT1SETL 7F40 Reserved EHT1SETH 7F41 ...
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... ECON2CLRL 7FEF ECON2CLRH 7FF0 ERXWMCLRL 7FF1 ERXWMCLRH 7FF2 EIECLRL 7FF3 EIECLRH 7FF4 EIDLEDCLRL 7FF5 EIDLEDCLRH 7FF6 EUDASTCLRL 7FF7 EUDASTCLRH 7FF8 EUDANDCLRL 7FF9 EUDANDCLRH 7FFA — 7FFB — 7FFC EIRCLRL 7FFD EIRCLRH 7FFE ECON1CLRL 7FFF ECON1CLRH 2010 Microchip Technology Inc. ...
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... EIRCLR 3FDE 3FCF ECON1CLR 3FDF Note 1: Bit Set and Bit Clear registers are not implemented for the base SFRs located between 3F40h and 3F4Fh. 2010 Microchip Technology Inc. ENC424J600/624J600 Name Addr Name EHT1SET 3FA0 Reserved EHT2SET 3FA1 ...
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TABLE 3-7: ENC424J600/624J600 REGISTER FILE SUMMARY High Byte (‘H’ Register) 8-Bit File Bit 7 Bit 6 Bit 5 Bit 4 Name 16-Bit Bit 15 Bit 14 Bit 13 Bit 12 EUDAST — User-Defined Area Start Pointer (EUDAST<14:8>) EUDAND — User-Defined ...
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TABLE 3-7: ENC424J600/624J600 REGISTER FILE SUMMARY (CONTINUED) High Byte (‘H’ Register) 8-Bit File Bit 7 Bit 6 Bit 5 Bit 4 Name 16-Bit Bit 15 Bit 14 Bit 13 Bit 12 MICMD — — — — MIREGADR — — — ...
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... When the write opera- tion has completed, the BUSY bit clears itself. The host controller should not start any MIISCAN, MIWR or MIIRD operations while the BUSY bit is set. the MIREGADR register selective bit writes are not 2010 Microchip Technology Inc. ...
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... PHREG<4:0>: MII Management PHY Register Address Select bits The address of the PHY register which MII Management read and write operations will apply to. 2010 Microchip Technology Inc. ENC424J600/624J600 After setting the MIISCAN bit, the MIRD register will automatically be updated every 25.6 s. There is no status information which can be used to determine when the MIRD registers are updated ...
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... Bit is cleared U-0 U-0 U-0 — — — U-0 R-0 R-0 — r NVALID U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2010 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 MIISCAN MIIRD bit Bit is unknown U-0 U-0 — ...
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TABLE 3-9: PHY REGISTER FILE SUMMARY File Name Bit 15 Bit 14 Bit 13 Bit 12 PHCON1 PRST PLOOPBK SPD100 ANEN PSLEEP PHSTAT1 r FULL100 HALF100 FULL10 PHANA ADNP r ADFAULT r ADPAUS1 ADPAUS0 PHANLPA LPNP LPACK LPFAULT r LPPAUS1 ...
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... DMA operations that may simultaneously 7A8Bh also be accessing the general purpose or receive buffer memory. 7C00h 7C1Fh 7C20h 7C2Fh 7C30h 7C3Fh 7C40h 7C4Fh SRAM BUFFER ORGANIZATION 0000h Buffer ERXST – 1 ERXST Buffer 5FFFh on 10Base-T and 2010 Microchip Technology Inc. ...
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... TRANSMIT BUFFER The ENC624J600 family does not implement a dedi- cated transmit buffer. The transmit hardware has the flexibility of transmitting data starting at any memory address, including odd memory addresses which are off of a 16-bit word boundary ...
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... Buffer Pointers 0000h Write EGPDATA Write ERXDATA General Purpose Buffer Read EUDADATA EUDADATA Write Read EGPDATA Circular RX FIFO Buffer Read ERXRDPT ERXDATA 5FFFh Unimplemented EGPWRPT ERXWRPT EUDARDPT EUDAWRPT ERXST – 1 ERXST EGPRDPT EUDAST EUDAND 2010 Microchip Technology Inc. ...
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... EGPRDPT/EGPWRPT = ERXST – 1, then EGPRDPT/EGPWRPT = 0000h else if EGPRDPT/EGPWRPT = 5FFFh, then EGPRDPT/EGPWRPT = 0000h else EGPRDPT/EGPWRPT = EGPRDPT/EGPWRPT + 1 2010 Microchip Technology Inc. ENC424J600/624J600 3.5.5.1 Circular Wrapping with EGPDATA Normally, operations involving EGPDATA cause the EGPRDPT or EGPWRPT Pointer to automatically increment by one byte address. However, if the end of the general purpose buffer area (ERXST – ...
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... If EUDAND is set to 5FFFh, the pointer address increments to the value of EUDAST, instead of 0000h. The increment behavior logic is explained in Equation 3-3. CIRCULAR BUFFER WRAPPING USING THE ERXDATA WINDOW 0000h General Purpose Buffer ERXST – 1 ERXST Circular RX FIFO Buffer 5FFFh Unimplemented 2010 Microchip Technology Inc. ...
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... Buffer 5FFFh Unimplemented Case 1: EUDAND > EUDAST Normal User-Defined Buffer 2010 Microchip Technology Inc. ENC424J600/624J600 user-defined area pointers will jump over the range of addresses between EUDAND and EUDAST. This is shown in Case 2. If the user-defined buffer is not needed, it can effectively be disabled by setting EUDAST and EUDAND to addresses outside of the implemented memory area ...
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... ENC424J600/624J600 NOTES: DS39935C-page 38 2010 Microchip Technology Inc. ...
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... SPI bus shared by multiple SPI slave devices that also high-impedance state when inactive. For details on the physical connections to the interface, see Section 2.7 “Host Interface Pins”. 2010 Microchip Technology Inc. ENC424J600/624J600 4.2 SPI Instruction Set The SPI interface supports a unique instruction set, consisting of 47 distinct opcodes ...
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... DDDD DDDD DDDD DDDD dddd dddd DDDD DDDD dddd dddd DDDD DDDD XXXX XXXX XXXX XXXX DDDD DDDD DDDD DDDD XXXX XXXX XXXX XXXX DDDD DDDD DDDD DDDD XXXX XXXX XXXX XXXX DDDD DDDD DDDD DDDD 2010 Microchip Technology Inc. ...
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... SCK Hi-Z x 2010 Microchip Technology Inc. ENC424J600/624J600 4.3.1 BxSEL OPCODES The bank select opcodes, B0SEL, B1SEL, B2SEL and B3SEL, switch the SFR bank to Bank 0, Bank 1, Bank 2 or Bank 3, respectively. The updated bank select state is saved internally inside the ENCX24J600 in volatile memory ...
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... RBSEL without deasserting the chip select line in between. Since this opcode does not modify the ENCX24J600 internal state, it can be aborted at any time by returning the CS pin to the inactive state SFR Bank Select Hi 2010 Microchip Technology Inc. ...
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... Microchip Technology Inc. ENC424J600/624J600 For write commands (shown in Figure 4-4), the opcode byte (‘011xxx00’) must be presented on the SI line, MSb first, followed immediately by the pointer data to be written. Like the data returned during a read operation, the write data must be presented MSb first, Least Significant Byte first ...
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... DDDD DDDD Write User-Defined Area Write Pointer (EUDAWRPT). WUDAWRPT 0111 0110 xxxx xxxx XXXX XXXX Read User-Defined Area Write Pointer (EUDAWRPT). RUDAWRPT Legend: x/d = pointer data (LSB), X/D = pointer data (MSB, optional). DS39935C-page 44 Argument 3rd Byte (EGPRDPT). (EGPRDPT). (EGPWRPT). (EGPWRPT). Instruction 2010 Microchip Technology Inc. ...
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... Hi 2010 Microchip Technology Inc. ENC424J600/624J600 bank prior to their execution. Because of this, they cannot be used for the unbanked SFR space (80h through 9Fh). Figure 4-5 shows the timing relationships for these operations. Like all other opcodes, data must be presented on the SI pin, MSb first. For all banked ...
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... BFC 101a aaaa dddd dddd by the application the time a have completed and cleared Argument 3rd Byte Nth Byte XXXX XXXX XXXX XXXX DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD 2010 Microchip Technology Inc. ...
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... Hi 2010 Microchip Technology Inc. ENC424J600/624J600 byte-wise on SO, MSb first. As with three-byte instructions, the lower byte of a data word is presented first, followed by the upper byte. As long as the CS pin is held low, the instruction continues to execute, automatically incrementing to the next register address in the SFR space and writing data from SI to, or outputting data on SO from, subsequent registers ...
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... AAAA AAAA BFSU 0010 0100 AAAA AAAA BFCU 0010 0110 AAAA AAAA the ERXHEADH:ERXHEADL Argument 3rd Byte Nth Byte xxxx xxxx XXXX XXXX dddd dddd DDDD DDDD dddd dddd DDDD DDDD dddd dddd DDDD DDDD 2010 Microchip Technology Inc. ...
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... SO Hi 2010 Microchip Technology Inc. ENC424J600/624J600 SO during SCK clocks, 1 through 8. Starting with the 9th clock, data is clocked out byte-wise on SO, MSb first. As long as the CS pin is held low, the instruction continues to execute, automatically incrementing to the next SRAM address according to the pointer wrapping rules described in Section 3.5.5 “ ...
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... WUDADATA 0011 0010 dddd dddd Argument 3rd Byte Nth Byte XXXX XXXX XXXX XXXX DDDD DDDD DDDD DDDD XXXX XXXX XXXX XXXX DDDD DDDD DDDD DDDD XXXX XXXX XXXX XXXX DDDD DDDD DDDD DDDD 2010 Microchip Technology Inc. ...
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... X 19 Note 1: Includes only address, data and port control strobes. INT/SPISEL and PSPCFG pins used for mode configuration are not included. 2010 Microchip Technology Inc. ENC424J600/624J600 tieing each of the PSPCFG<4:0> pins to either The available combinations along with relative SS performance metrics are summarized in Table 5-1. ...
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... UNUSED INTERFACE PINS Any unused PSP pins are placed in a high-impedance state, regardless of the state of the CS pin. For maximum ESD performance recommended that unused interface pins not be allowed to float. Instead recommended that unused interface pins be tied to either 2010 Microchip Technology Inc. ...
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... Each of the modes is described in detail in the following sections. 2010 Microchip Technology Inc. ENC424J600/624J600 5.3.1 MODE 1 PSP Mode 8-bit, fully demultiplexed mode that is available on 64-pin devices only. The parallel inter- face consists of 8 bi-directional data pins (AD< ...
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... DS39935C-page 54 (1) CS PMCSx RD PMRD WR PMWR 6 A<14:9> 9 A<8:0> 8 AD<7:0> (3) INT/SPISEL INTx 100 k PSPCFG2 PSPCFG3 PSPCFG4 T PSP4 Address<14:0> Data<7:0> Hi PSP2 PSP3 T T PSP8 PSP11 Address<14:0> Address<14:0> T PSP9 Data<7:0> T Data<7:0> PSP10 ENC624J600 ( when only indirect DD Data<7:0> Hi-Z Hi-Z 2010 Microchip Technology Inc. ...
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... Strobe the EN signal high and then low. Sample timing diagrams for reading and writing data in this mode are provided in Figure 5-5 and Figure 5-6, respectively. (1) CS PMCSx R/W EN PMENB 6 A<14:9> 9 A<8:0> 8 AD<7:0> (3) INT/SPISEL INTx +3.3V 100 k PSPCFG2 PSPCFG3 PSPCFG4 ENC624J600 ( when only indirect DD DS39935C-page 55 ...
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... Hi-Z FIGURE 5-6: MODE 2 WRITE OPERATION TIMING (TWO BYTES PSP5 R/W EN A<14:0> T PSP6 AD<7:0> Hi-Z T PSP7 DS39935C-page 56 T PSP4 Address<14:0> Address<14:0> Data<7:0> Hi PSP2 PSP3 T T PSP8 PSP11 Address<14:0> Address<14:0> T PSP9 Data<7:0> Data<7:0> T PSP10 Data<7:0> Hi-Z Hi-Z 2010 Microchip Technology Inc. ...
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... WRH simultaneously. Sample timing diagrams for reading and writing data in this mode are provided in Figure 5-8 and Figure 5-9, respectively. (1) CS PMCSx RD PMRD WRL PMWRL (2) WRH 6 A<13:8> 8 A<7:0> 16 AD<15:0> (4) INT/SPISEL INTx +3.3V 100 k PSPCFG2 PSPCFG3 PSPCFG4 ENC624J600 (2) ( when only indirect DD DS39935C-page 57 ...
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... Hi-Z FIGURE 5-9: MODE 3 WRITE OPERATION TIMING (THREE BYTES PSP5 RD WRL WRH A<13:0> T PSP6 AD<15:0> Hi-Z T PSP7 DS39935C-page 58 T PSP4 Address<13:0> Data<15:0> Hi PSP2 PSP3 T T PSP8 PSP11 Address<13:0> T Address<13:0> PSP9 Data<15:0> Data<7:0> T PSP10 Data<15:0> Hi-Z Hi-Z 2010 Microchip Technology Inc. ...
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... B1SEL simultaneously. Sample timing diagrams for reading and writing data in this mode are provided in Figure 5-11 and Figure 5-12, respectively. (1) CS PMCSx R/W B0SEL (2) B1SEL 6 A<13:8> 8 A<7:0> 16 AD<15:0> (4) INT/SPISEL INTx +3.3V 100 k PSPCFG2 PSPCFG3 PSPCFG4 ENC624J600 (2) ( when only indirect DD DS39935C-page 59 ...
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... FIGURE 5-12: MODE 4 WRITE OPERATION TIMING (THREE BYTES PSP5 R/W B0SEL B1SEL A<13:0> T PSP6 AD<15:0> Hi-Z T PSP7 DS39935C-page 60 T PSP4 Address<13:0> Address<13:0> Data<15:0> Hi PSP2 PSP3 T T PSP8 PSP11 Address<13:0> Address<13:0> T PSP9 Data<15:0> Data<7:0> T PSP10 Data<15:0> Hi-Z Hi-Z 2010 Microchip Technology Inc. ...
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... Selecting PSP Mode 5 differs between 44-pin and 64-pin devices, as shown in Figure 5-13. For the 44-pin ENC424J600, tie PSPCFG0 For the 64-pin SS ENC624J600, tie PSPCFG1 and PSPCFG2 to V and PSPCFG3 This mode uses active-high Read and Write (RD and WR) strobes, as well as separate Chip Select and Address Latch (CS and AL) lines ...
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... PMALL 6 AD<14:9> PMA<14:9> PMA8 AD8 8 AD<7:0> PMD<7:0> (3) INT/SPISEL INTx 100 k PSPCFG0 CS PMCSx RD PMRD WR PMWR AL PMALL 6 AD<14:9> PMA<14:9> PMA8 AD8 8 AD<7:0> PMD<7:0> (3) INT/SPISEL INTx +3.3V 100 k PSPCFG1 PSPCFG2 PSPCFG3 ENC424J600 (1) (2) ENC624J600 (1) ( when only indirect DD 2010 Microchip Technology Inc. ...
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... PSP13 (1) AD<14:9> Address<14:9> (1) AD8 Address<8> AD<7:0> Hi-Z Address<7:0> T PSP12 Note 1: AD8 must be driven by the host controller. AD<14:9> may be tied to logic high when only indirect access is desired. 2010 Microchip Technology Inc. ENC424J600/624J600 T PSP4 T PSP15 Data<7:0> Hi PSP2 PSP3 T PSP14 T T PSP8 PSP11 Data< ...
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... Selecting PSP Mode 6 differs between 44-pin and 64-pin devices, as shown in Figure 5-16. For the 44-pin ENC424J600, tie PSPCFG0 For the 64-pin DD ENC624J600, tie PSPCFG1 and PSPCFG3 to V and PSPCFG2 This mode uses a combined Read/Write (R/W) select, an Enable (EN) strobe and separate Chip Select (CS) and Address Latch (AL) lines ...
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... PMALL 6 PMA<14:9> PMA8 8 PMD<7:0> (3) INTx +3.3V 100 k PMCSx PMRD/PMWR PMENB PMALL 6 PMA<14:9> PMA8 8 PMD<7:0> (3) INTx +3.3V 100 k ENC424J600 ( (2) AD<14:9> AD8 AD<7:0> INT/SPISEL PSPCFG0 ENC624J600 ( (2) AD<14:9> AD8 AD<7:0> INT/SPISEL PSPCFG1 PSPCFG2 PSPCFG3 . DD when only indirect DD DS39935C-page 65 ...
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... Note 1: AD8 must be driven by the host controller. AD<14:9> may be tied to logic high when only indirect access is desired . DS39935C-page 66 T PSP1 T PSP4 T PSP15 Data<7:0> Hi PSP2 PSP3 T PSP14 T PSP5 T T PSP8 PSP11 Data<7:0> T PSP7 T T PSP14 PSP10 Data<7:0> Hi-Z Data<7:0> Hi-Z 2010 Microchip Technology Inc. ...
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... WRH without going through another address latch cycle. Sample timing diagrams for reading and writing data in this mode are provided in Figure 5-20 and Figure 5-21, respectively. (1) CS PMCSx RD PMRD WRL PMWRL (2) WRH AL PMALL 16 AD<15:0> (3) INT/SPISEL INTx +3.3V 100 k PSPCFG1 PSPCFG2 PSPCFG3 ENC624J600 ( DS39935C-page 67 ...
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... MODE 9 WRITE OPERATION TIMING (THREE BYTES – SAME ADDRESS PSP12 RD WRL WRH AL T PSP13 AD<15:0> Hi-Z Address<13:0> T PSP12 DS39935C-page 68 T PSP4 T PSP15 Data<15:0> Hi PSP2 PSP3 T PSP14 T T PSP8 PSP11 Data<15:0> T PSP7 T T PSP14 PSP10 Data<15:0> Hi-Z Data<7:0> Hi-Z 2010 Microchip Technology Inc. ...
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... If a subsequent read or write of the same memory address is desired possible to restrobe B0SEL or B1SEL without going through another address latch cycle. Sample timing diagrams for reading and writing data in this mode are provided in Figure 5-23 and Figure 5-24, respectively. ENC624J600 (1) CS PMCSx R/W B0SEL PMENB0 ...
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... MODE 10 WRITE OPERATION TIMING (THREE BYTES – SAME ADDRESS PSP12 R/W B0SEL B1SEL AL T PSP13 AD<15:0> Hi-Z Address<13:0> T PSP12 DS39935C-page 70 T PSP1 T PSP4 T PSP15 Data<15:0> Hi PSP2 PSP3 T PSP14 T PSP5 T T PSP8 PSP11 Data<15:0> PSP7 PSP14 PSP10 Data<15:0> Hi-Z Data<7:0> Hi-Z 2010 Microchip Technology Inc. ...
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... Used in the Calculation of the FCS 46-1500 4 Note 1: The FCS is transmitted starting with bit 31 and ending with bit 0. 2010 Microchip Technology Inc. ENC424J600/624J600 6.1.1 START OF STREAM/PREAMBLE AND START-OF-FRAME DELIMITER When using ENC424J600/624J600 devices, the start of stream/preamble and Start-Of-Frame delimiter fields are automatically generated for transmitted frames and stripped from received ones ...
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... When receiving devices accept and write the CRC field to the receive buffer. Frames with invalid CRC values can be discarded by the CRC Error Rejection filter, described in Section 10.3 “CRC Error Rejection Filter” . frames, ENC424J600/624J600 2010 Microchip Technology Inc. ...
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... POR System Reset (ETHRST) Transmit Reset (TXRST) Receive Reset (RXRST) PHY Reset (PRST) 2010 Microchip Technology Inc. ENC424J600/624J600 7.2 System Reset A System Reset reverts all registers back to their default Reset values, COCON<3:0> (ECON2<11:8>), which controls the frequency output on CLKOUT. All transmit, receive, MAC, PHY, DMA and cryptographic logic are reset ...
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... The POR and System Resets automatically perform a PHY Reset, so this step does not need to be performed after a System or Power-on Reset. Only the PHY is affected by this operation. Other register and control blocks are not affected by this event. 2010 Microchip Technology Inc. ...
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... CLKOUT after a POR is 4 MHz. The last programmed frequency is maintained after all other Reset events. For more information on using the output of the CLKOUT pin, see Section 2.2 “CLKOUT Pin” . 2010 Microchip Technology Inc. ENC424J600/624J600 8.3 Receive Buffer Before packet reception is enabled, the receive buffer must be configured by programming the ERXST Pointer ...
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... Most applications will program this register to 15h, which represents the minimum IEEE 802.3 specified Inter-Packet Gap (IPG) of 0.96 s (at 100 Mb/s) or 9.6 s (at 10 Mb/s). 2010 Microchip Technology Inc. details about speed/duplex FULDPX ...
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... Transmit logic is held in Reset. TXRTS (ECON1<1>) is automatically cleared by hardware when this bit is set Transmit logic is not in Reset (normal operation) Note 1: Reset value on POR events only. All other Resets leave these bits unchanged. 2010 Microchip Technology Inc. ENC424J600/624J600 (1) (1) R/W-0 R/W-1 ...
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... AESLEN<1:0>: AES Key Length Control bits 11 = Reserved 10 = 256-bit key 01 = 192-bit key 00 = 128-bit key Note 1: Reset value on POR events only. All other Resets leave these bits unchanged. DS39935C-page 78 2010 Microchip Technology Inc. ...
Page 81
... Display link state; pin is driven high when linked 0001 = On (pin is driven high) 0000 = Off (pin is driven low) bit 7-5 DEVID<2:0>: Device ID bits 001 = ENC624J600 family device bit 4-0 REVID<4:0>: Silicon Revision ID bits Indicates current silicon revision. Note 1: These configurations require that a bi-color LED be connected between the LEDA and LEDB pins, and that LACFG< ...
Page 82
... No proprietary header is present; the CRC covers all data (normal operation) DS39935C-page 80 R/W-0 U-0 U-0 NOBKOFF — — R/W-1 R/W-0 R/W-0 TXCRCEN PHDREN HFRMEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W bit 8 R/W-1 R/W-0 r FULDPX bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 83
... The register value should be programmed to the desired period in nibble times minus 6. The recommended setting is 12h which represents the minimum IEEE specified Inter-Packet Gap (IPG) of 0.96 s (at 100 Mb/s) or 9.6 s (at 10 Mb/s). 2010 Microchip Technology Inc. ENC424J600/624J600 U-0 ...
Page 84
... U-0 R/W-1 R/W-1 — MAXRET3 MAXRET2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W bit 8 R/W-1 R/W-0 IPG1 IPG0 bit Bit is unknown R/W-1 R/W bit 8 R/W-1 R/W-1 MAXRET1 MAXRET0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 85
... MAC address from the MAADR registers into the transmitted byte stream, then continues reading and transmitting the remaining bytes from memory. 2010 Microchip Technology Inc. ENC424J600/624J600 FIGURE 9-1: EXAMPLES OF TX BUFFER WRAPPING ...
Page 86
... MAC address insertion enabled (TXMAC = 1 ) Automatic padding disabled (PADCFG<2:0> = 000 ) CRC generation enabled (TXCRCEN = 1 ) 012Ah 0150h ... ... Data Next Packet MAC insertion enabled (TXMAC = 1 ) Automatic padding enabled (PADCFG<2:0> = 101 ) CRC generation enabled (TXCRCEN = 1 ) 015Bh ... Padding Next Packet ... 2010 Microchip Technology Inc. ...
Page 87
... Full-Duplex mode.) The device asserts these flags and clears the TXRTS bit to prevent a single packet from stalling device operation. When 2010 Microchip Technology Inc. ENC424J600/624J600 any of these flags are set, the packet was not success- fully transmitted and the host controller should determine whether to retry or ignore the error. The CRCBAD (EXTSTAT< ...
Page 88
... ERXHEAD Pointer is rolled back to its previous location and the packet is discarded. ... ... ... ... ... Free byte for incoming data Byte protected from incoming data Dummy byte, skip when reading XX 2010 Microchip Technology Inc. 5FFFh T XX ...
Page 89
... Section 13.1.5 “Received Packet Alternatively, poll the PKTCNT bits for a non-zero value. 2010 Microchip Technology Inc. ENC424J600/624J600 9.2.2 STORAGE OF INCOMING PACKETS Packets are stored sequentially in the receive buffer. Each frame is stored as it was presented to the MAC, ...
Page 90
... PAD PAD 0162h PAD PAD 0164h FCS[2] FCS[3] 0166h FCS[0] FCS[1] 0168h XX XX 016Ah RSV[1] RSV[0] 016Ch RSV[3] RSV[2] 016Eh RSV[5] RSV[ ERXTAIL Pointer to Next Packet Receive Status Vector Destination Address Source Address Start of Next Packet 2010 Microchip Technology Inc. ...
Page 91
... Reserved 16 Packet Previously Ignored 1 15:0 Received Byte Count 0 2010 Microchip Technology Inc. ENC424J600/624J600 Description 00h ‘ 0 ’ Current frame met criteria for the Unicast Receive filter. Current frame met criteria for the Pattern Match Receive filter as configured when the packet was received. ...
Page 92
... Flow control disabled/Idle 00 DS39935C-page 90 R/W-0 R/W-0 R/W-0 HASHLST AESST AESOP1 R/W-0 R/W-0 R/W-0 DMACPY DMACSSD DMANOCS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 AESOP0 PKTDEC bit 8 R/W-0 R/W-0 TXRTS RXEN bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 93
... TXRTS: Transmit Request to Send Status/Control bit 1 = Transmit an Ethernet frame; automatically cleared by hardware when done 0 = Transmit logic done/Idle bit 0 RXEN: Receive Enable bit 1 = Packets which pass the current RX filter configuration are written to the receive buffer 0 = All packets received are ignored 2010 Microchip Technology Inc. ENC424J600/624J600 DS39935C-page 91 ...
Page 94
... Applicable in Half-Duplex mode only; collisions and deferrals are not possible in Full-Duplex mode. DS39935C-page 92 R-0 R-0 R LATECOL R-0 R-0 R-0 (1) CRCBAD COLCNT3 COLCNT2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) (1) (1) R-0 R-0 (1) (1) (1) MAXCOL EXDEFER bit 8 R-0 R-0 (1) (1) (1) COLCNT1 COLCNT0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 95
... No Ethernet link present bit 7-0 PKTCNT<7:0>: Receive Packet Count bits Number of complete packets that are saved in the RX buffer and ready for software processing. Set the PKTDEC (ECON1<8>) bit to decrement this field. 2010 Microchip Technology Inc. ENC424J600/624J600 R-0 R-0 R-0 CLKRDY ...
Page 96
... ENC424J600/624J600 NOTES: DS39935C-page 94 2010 Microchip Technology Inc. ...
Page 97
... Similarly, Rejection filters either discard frames or defer to lower priority filters. Frames that pass through all filters without specifically being accepted are discarded. Figure 10-1 demonstrates this decision tree. 2010 Microchip Technology Inc. ENC424J600/624J600 At power-up, the CRC Error Rejection, Runt Error Rejection, Unicast Collection and Broadcast Collection filters are enabled, and all others are disabled ...
Page 98
... R/W-0 NOTPM PMEN3 PMEN2 R/W-1 R/W-1 R/W-0 RUNTEN UCEN NOTMEEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) (1) (1) (1) (1) R/W-0 R/W-0 PMEN1 PMEN0 bit 8 R/W-0 R/W-1 MCEN BCEN bit Bit is unknown (1) (1) (1) (1) 2010 Microchip Technology Inc. ...
Page 99
... This filtering decision can be overridden by the CRC Error Rejection filter and Runt Error Rejection filter decisions, if enabled, by CRCEN or RUNTEN. 2: This filtering decision can be overridden by the CRC Error Collection filter and Runt Error Collection filter decisions, if enabled, by CRCEEN or RUNTEEN. 2010 Microchip Technology Inc. ENC424J600/624J600 (2) (2) (1) ...
Page 100
... Disabled No CRC is valid? Yes Yes Length < 64 bytes? No Yes Unicast for me? No Yes Unicast for someone else? No Yes Multicast destination? No Yes Broadcast destination? No Yes Hash Table bit set? No Yes Magic Packet™ for me? No Accept Packet 2010 Microchip Technology Inc. ...
Page 101
... CRC. When enabled, the CRC Error Rejection filter will discard these truncated frames, as well as collision fragments, and other frames that become corrupted during transmission. 2010 Microchip Technology Inc. ENC424J600/624J600 This filter is enabled at power-up. To disable this filter, clear CRCEN (ERXFCON<6>). If the filter is disabled, all frames will be passed on to the next lower priority filter, regardless of CRC validity ...
Page 102
... Result of CRC-32 with 4C11DB7h: 1101 1010 0000 1011 0100 0101 0111 0101 (binary) Pointer Derived from bits<28:23> of CRC Result: 110100 (binary (hex) Corresponding Hash Table Location: EHT4<4> Bit Numbers in Hash Table DERIVING A HASH TABLE LOCATION 2010 Microchip Technology Inc. ...
Page 103
... 2010 Microchip Technology Inc. ENC424J600/624J600 Packet. This pattern may be located anywhere within the packet. Other fields in the packet, such as the destination address or bytes preceding or following the Magic Packet pattern, are ignored. This filter is disabled at power-up. To enable this filter, set MPEN (ERXFCON<14>). If the filter is disabled or the received packet is not a Magic Packet, the frame will be passed to the next lower priority filter ...
Page 104
... To accept absolutely all recognizable Ethernet frames, including those (MACCON1<1>) to ‘ 1 ’ and set UCEN, NOTMEEN and MCEN in ERXFCON. In any mode, frames which cannot fit in the receive buffer, or would cause the PKTCNT field (ESTAT<7:0>) to overflow, are still discarded. with errors, set PASSALL 2010 Microchip Technology Inc. ...
Page 105
... Bytes used for Checksum Computation Values used for Checksum Computation = {88h, AAh, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 00h} (00h padding byte added by hardware) Note: Received data is shown in hexadecimal. Byte numbers are shown in decimal format. 2010 Microchip Technology Inc. ENC424J600/624J600 SA Type/Length ...
Page 106
... ENC424J600/624J600 NOTES: DS39935C-page 104 2010 Microchip Technology Inc. ...
Page 107
... This limitation of flow control in half-duplex operation cannot be avoided. 2010 Microchip Technology Inc. ENC424J600/624J600 Given the detrimental effect that back pressure based flow control inflicts on a network, along with the ...
Page 108
... FCOP<1:0> bits to the automatic flow control hardware. Note: Setting RXFWM to be equal to RXEWM (i.e., no hysteresis between full and empty) is not permitted. For automatic flow control to operate correctly, RXEWM must always be at least one less than RXFWM, implying at least 96 bytes of hysteresis. 2010 Microchip Technology Inc. ...
Page 109
... PASSALL: Pass All Received Frames Enable bit 1 = Control frames received by the MAC are written into the receive buffer if not filtered out 0 = Control frames are discarded after being processed by the MAC (normal operation) bit 0 Reserved: Write as ‘ 1 ’ 2010 Microchip Technology Inc. ENC424J600/624J600 U-0 R/W-0 R/W-0 — ...
Page 110
... ENC424J600/624J600 NOTES: DS39935C-page 108 2010 Microchip Technology Inc. ...
Page 111
... SPD100 to select 10Base-T mode. Set the PFULDPX bit (PHCON1<8>) to configure Full-Duplex mode or clear PFULDPX to use half-duplex operation. 2010 Microchip Technology Inc. ENC424J600/624J600 After reconfiguring the Speed and Duplex modes, update the MACON2, MACLCON, MAIPG and MABBIPG registers as described in Section 8.9 “ ...
Page 112
... MACON2, MACLCON, MAIPG and MABBIPG registers as described in Section 8.9 “After Link Establishment” . R/W-1 R/W-0 R/W-0 (1) ANEN PSLEEP R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) R/W-0 R/W-0 (1) r RENEG PFULDPX bit 8 R-0 R-0 R bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 113
... Reserved: Ignore on read bit 0 EXTREGS: Extended Capabilities Registers Present Status bit 1 = PHY has extended capability registers at addresses, 16 thru 31 Note 1: This is the only valid state for this bit; a ‘ 0 ’ represents an invalid condition. 2010 Microchip Technology Inc. ENC424J600/624J600 (1) (1) R-1 R-1 ...
Page 114
... Bit is cleared R-0 R/W-0 R/W R-0 R-0 R-0 SPDDPX2 SPDDPX1 SPDDPX0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-x R/W bit 8 R-1 R bit Bit is unknown R/W-0 R/W bit 8 R/W-0 R/W bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 115
... Local PHY is incapable of 10Base-T half-duplex operation bit 4-0 ADIEEE<4:0>: Advertise IEEE Standard Selector Field bits 00001 = IEEE 802.3 Std. All other values reserved by IEEE. Always specify a selector value of ‘ 00001 ’ for this device. 2010 Microchip Technology Inc. ENC424J600/624J600 R-0 R/W-0 R/W-0 ...
Page 116
... All other values are reserved by IEEE. Remote node should also specify this as the selector value. DS39935C-page 114 R-0 R-0 R-0 r LPPAUS1 LPPAUS0 R-0 R-0 R-0 LPIEEE4 LPIEEE3 LPIEEE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-0 R-0 LP100T4 LP100FD bit 8 R-0 R-0 LPIEEE1 LPIEEE0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 117
... PHANLPA register has been written with a new value from the link partner; automatically cleared when register is read 0 = PHANLPA contents have not changed since the last read of PHANE bit 0 LPANABL: Link Partner Auto-Negotiation Able Status bit 1 = Link partner implements auto-negotiation 0 = Link partner does not implement auto-negotiation 2010 Microchip Technology Inc. ENC424J600/624J600 R-0 R-0 R ...
Page 118
... ENC424J600/624J600 NOTES: DS39935C-page 116 2010 Microchip Technology Inc. ...
Page 119
... TXABTIE RXABTIF RXABTIE PCFULIF PCFULIE 2010 Microchip Technology Inc. ENC424J600/624J600 When an enabled interrupt occurs, the INT pin remains low until all flags causing interrupts are cleared or masked off (the enable bit is cleared). If more than one interrupt source is enabled, the host controller must poll each flag to determine the source(s) of the interrupt ...
Page 120
... TXRTS (ECON1<1>) has been cleared by hardware interrupt pending DS39935C-page 118 R/W-0 R/W-1 R/W-0 AESIF LINKIF r R-0 R/W-0 R/W-0 r TXIF TXABTIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W bit 8 R/W-0 R/W-0 RXABTIF PCFULIF bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 121
... PKTCNT field is saturated at FFh interrupt pending bit 0 PCFULIF: Packet Counter Full Interrupt Flag bit 1 = PKTCNT field has reached FFh. Software must decrement the packet counter to prevent the next RX packet from being dropped interrupt pending 2010 Microchip Technology Inc. ENC424J600/624J600 DS39935C-page 119 ...
Page 122
... This bit is read-only and cannot be cleared. Hardware does not modify it. DS39935C-page 120 R/W-0 R/W-0 R/W-0 AESIE LINKIE r R-1 R/W-0 R/W-0 (1) r TXIE TXABTIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W bit 8 R/W-0 R/W-0 RXABTIE PCFULIE bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 123
... To enable the AES complete interrupt, set AESIE (EIE<12>). For more information on the Advanced Encryption Standard engine, refer to Section 15.3 “Advanced Encryption Standard (AES)” . 2010 Microchip Technology Inc. ENC424J600/624J600 13.1.4 LINK CHANGE The link change interrupt occurs when the PHY link status changes ...
Page 124
... When the host wakes up, it needs to restore the normal filter configuration and continue performing its tasks. For more details about the Magic Packet filter, refer to Section 10.10 “Magic Packet™ Collection Filter” . 2010 Microchip Technology Inc. RUNTEN ...
Page 125
... Microchip Technology Inc. ENC424J600/624J600 It is recommended that DMA configuration parameters (such as address pointers and operation selection bits) not be modified while DMAST (ECON1< ...
Page 126
... Mbytes/second when the source and destination addresses share the same alignment. Differing source and destination alignment would slow the process to 33.3 Mbytes/second. Worst case conditions can cut the DMA throughput by no more than half of the typical values. 2010 Microchip Technology Inc. ...
Page 127
... The MD5/SHA-1 hashing module remains regardless of the CRYPTEN state. 2010 Microchip Technology Inc. ENC424J600/624J600 15.1 Modular Exponentiation Modular Exponentiation is the base function for the RSA and Diffie-Hellman algorithms used in public key cryptography. This module computes the value mod M , where 0 ...
Page 128
... Using this bit to load a previously saved context is described in Section 15.2.3 “Context Switching” . The value of the HASHOP bit may not be changed once the HASHEN bit is set must be configured first. 2010 Microchip Technology Inc. the Modular Time ...
Page 129
... To allow for hashes to be computed over any length of data, the integral length of 4 restriction does not apply to the last transfer (when HASHLST is set). 2010 Microchip Technology Inc. ENC424J600/624J600 15.2.1 MD5 HASHING The module implements the MD5 function, as described in the Internet Engineering Task Force RFC 1321, “ ...
Page 130
... After the context has been saved, the module may be used for a different type of hash (MD5 instead of SHA-1, or vice versa). When loading a context back into the module, verify that SHA1MD5 (ECON2<12>) selects the correct hash operation. 2010 Microchip Technology Inc. ...
Page 131
... Microchip Technology Inc. ENC424J600/624J600 15.2.4 MD5/SHA-1 HASH PERFORMANCE The implications noted in Section 15.2.1 “MD5 Hash- ing” ...
Page 132
... Figure 15-1 shows the use of ECB mode for encryption and decryption. Ciphertext 1 0 Key DATA KEY DECRYPTER Ciphertext Plaintext 1 Electronic Code Book Mode (ECB) DECRYPTION Ciphertext 1 Key Key KEY DATA KEY DECRYPTER Plaintext 0 1 2010 Microchip Technology Inc. ...
Page 133
... Plaintext 0 IV Key DATA KEY ENCRYPTER Ciphertext 0 2010 Microchip Technology Inc. ENC424J600/624J600 5. Wait for the hardware to clear AESST. 6. Read the plaintext message from TEXTA at 7C20h. 7. Repeat steps 3 through 6 for subsequent blocks. The context for ECB mode includes only the encryption key ...
Page 134
... Other less common implemen- tations, including 1-bit and 8-bit CFB modes, could be accomplished with support software, but are not detailed here. Key Key IV KEY DATA KEY ENCRYPTER 1 Plaintext 1 0 DECRYPTION Key DATA KEY ENCRYPTER Ciphertext Ciphertext 1 0 Plaintext 1 2010 Microchip Technology Inc. ...
Page 135
... ENCRYPTION IV Key DATA KEY DATA ENCRYPTER ENCRYPTER Plaintext Plaintext 0 Ciphertext 0 2010 Microchip Technology Inc. ENC424J600/624J600 3. Copy the Initialization Value (IV) to TEXTA at 7C20h. 4. Set AESST to initiate the encryption. 5. Copy the ciphertext message to TEXTB at 7C30h. 6. Wait for the hardware to clear AESST. 7. Read the plaintext message from XOROUT at 7C40h ...
Page 136
... Figure 15-5 shows the use of CTR mode for encryption and decryption. Key CTR 0 KEY DATA ENCRYPTER Ciphertext 1 Ciphertext Plaintext 1 Counter Mode (CTR) DECRYPTION Key CTR Key 1 KEY DATA KEY ENCRYPTER Ciphertext 0 1 Plaintext 0 1 2010 Microchip Technology Inc. ...
Page 137
... Wait for the hardware to clear AESST. 7. Read the ciphertext message from XOROUT at 7C40h. 8. Repeat steps 3 through 7 for subsequent blocks. 2010 Microchip Technology Inc. ENC424J600/624J600 To decrypt a block using CTR mode: 1. Load the encryption key as described in Section 15.3.1 “Key Support” . Note that this mode does not make use of a decryption key ...
Page 138
... ENC424J600/624J600 NOTES: DS39935C-page 136 2010 Microchip Technology Inc. ...
Page 139
... Care should be taken to modify only the PSLEEP bit. 3. Restore receive capabilities by setting RXEN (ECON1<0>). 2010 Microchip Technology Inc. ENC424J600/624J600 After leaving Sleep mode, there will be a delay of several hundred milliseconds before a new link is established. If the host controller attempts to transmit ...
Page 140
... MOSFET on the power supply pins using a regulator with output enable capabilities. Keep in mind that an externally controlled power- down will require the ENCX24J600 to be completely re-initialized, as described in Section 8.0 “Initialization” . 2010 Microchip Technology Inc. ...
Page 141
... Energy detect circuit has detected energy on the TPIN+/- pins within the last 256 energy has been detected on the TPIN+/- pins within the last 256 ms bit 0 Reserved: Write as ‘ 0 ’, ignore on read Note 1: Intended for testing purposes only. Do not use in 10 Mbps operation. 2010 Microchip Technology Inc. ENC424J600/624J600 R/W-0 R/W-0 R/W-0 r ...
Page 142
... ENC424J600/624J600 NOTES: DS39935C-page 140 2010 Microchip Technology Inc. ...
Page 143
... Exposure to maximum rating conditions for extended periods may affect device reliability. 2010 Microchip Technology Inc. ENC424J600/624J600 and V , with respect to V ...
Page 144
... JA JA ) numbers are achieved by package simulations Min Typ Max Unit -40 — +125 °C -40 — +85 ° INT (T – Typ Max Unit Notes 28 — °C/W (Note 1) 49.8 — °C/W (Note 1) 47 — °C/W (Note 1) 2010 Microchip Technology Inc. ...
Page 145
... Excludes TX transformer center tap and LEDA/LEDB currents; cryptographic engine module disabled (EIR<15> Cryptographic engine module disabled (EIR<15> auto-negotiation disabled (PHCON1<12> and Ethernet disabled (ECON2<15> Measured across 100Ω termination on cable side of transformer. 2010 Microchip Technology Inc. ENC424J600/624J600 Standard Operating Conditions: -40°C T 85°C, 3.0V V 3.6V (Industrial) A ...
Page 146
... DD Units Conditions 34 mA PHCON2<13> PHCON1<11> (Note 3) 2.8 V (Note 3) mV Units Comments V F Capacitor must have low series resistance (< 3 Conditions Transformer Center Tap = 3. bias 0 MHz 2010 Microchip Technology Inc. ...
Page 147
... CLKOUT Pin Rise Time r CLKOUT t CLKOUT Pin Fall Time f CLKOUT CLKOUT Stability (jitter) CLKOUT Note 1: Measured from 0 0 2010 Microchip Technology Inc. ENC424J600/624J600 Standard Operating Conditions -40°C T +85°C, 3.00V Min Max Units 25 25 ...
Page 148
... Don’t Care Min Typ Max DC — — — — 50 — — 20 — — 10 — — 10 — — — — 10 — — CSD T CSH T DIS LSb Out Units Conditions MHz % Load on SO pin = Load on SO pin = 30 pF 2010 Microchip Technology Inc. ...
Page 149
... WR, WRL, WRH, EN, BxSEL PSP Deassertion Time T 12 CS, Address Setup Time PSP Assertion Time PSP T 14 Address Hold Time PSP Deassertion Time PSP 2010 Microchip Technology Inc. ENC424J600/624J600 Min Typ Max Units 1 — — ns — — — 4.5 — — ...
Page 150
... ENC424J600/624J600 NOTES: DS39935C-page 148 2010 Microchip Technology Inc. ...
Page 151
... In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2010 Microchip Technology Inc. ENC424J600/624J600 Example ENC424J600 -I/ 1010017 Example ENC424J600 -I/ 1010017 Example ENC624J600 -I/ 1010017 DS39935C-page 149 ...
Page 152
... ENC424J600/624J600 18.2 Package Details The following sections give the technical details of the packages. /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± %RG\ >4)1@ 1RWH 1RWHV DS39935C-page 150 2010 Microchip Technology Inc. ...
Page 153
... PP %RG\ >4)1@ 1RWH 2010 Microchip Technology Inc. ENC424J600/624J600 DS39935C-page 151 ...
Page 154
... ENC424J600/624J600 /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± 1RWH β 1RWHV DS39935C-page 152 [ [ PP %RG\ PP >74)3@ α φ 2010 Microchip Technology Inc. ...
Page 155
... Microchip Technology Inc. ENC424J600/624J600 [ [ PP %RG\ PP >74)3@ DS39935C-page 153 ...
Page 156
... ENC424J600/624J600 /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± 1RWH β 1RWHV DS39935C-page 154 [ [ PP %RG\ PP >74)3@ φ 2010 Microchip Technology Inc. α ...
Page 157
... Microchip Technology Inc. ENC424J600/624J600 [ [ PP %RG\ PP >74)3@ DS39935C-page 155 ...
Page 158
... ENC424J600/624J600 NOTES: DS39935C-page 156 2010 Microchip Technology Inc. ...
Page 159
... Removed preliminary from the data sheet. Section 1.0 “Device Overview” and Section 7.0 “Reset” had minor edits. Revision C (January 2010) Section 5.3.3 “MODE 3” and Section 5.3.4 “MODE 4” had minor edits. 2010 Microchip Technology Inc. ENC424J600/624J600 DS39935C-page 157 ...
Page 160
... ENC424J600/624J600 NOTES: DS39935C-page 158 2010 Microchip Technology Inc. ...
Page 161
... Counter Mode (CTR) ........................................ 134 Electronic Code Book Mode (ECB) .................. 130 Output Feedback Mode (OFB) ......................... 133 MD5/SHA-1 Hashing................................................. 126 Context Switching ............................................. 128 Modular Exponentiation ............................................ 125 2010 Microchip Technology Inc. ENC424J600/624J600 Customer Change Notification Service............................. 162 Customer Notification Service .......................................... 162 Customer Support............................................................. 162 D DC Characteristics ENC424J600/624J600 (Industrial) ...
Page 162
... Receiving Packets ........................................................ 86–87 Configuring Reception ................................................ 87 ERXHEAD/ERXTAIL Buffer Wrap (example) ............. 86 Incoming Packet Storage............................................ 87 Receive Status Vector ................................................ 89 Receive Status Vector (RSV) ..................................... 87 Received Packet in Buffer Memory (example) ........... 88 Status Vectors ............................................................ 89 Register Maps CLR (8-Bit PSP).......................................................... 24 SET (8-Bit PSP).......................................................... 23 SET/CLR (16-Bit PSP)................................................ 25 2010 Microchip Technology Inc. ...
Page 163
... N-Byte Instructions Banked SFR ....................................................... 45 SRAM Buffer ....................................................... 49 Unbanked SFR ................................................... 47 Single Byte Instructions .............................................. 41 Summary Table........................................................... 40 Three-Byte Instructions............................................... 43 Two-Byte Instructions ................................................. 42 2010 Microchip Technology Inc. ENC424J600/624J600 SRAM Buffer....................................................................... 32 Buffer Pointers............................................................ 34 Circular Wrapping ERXDATA Pointer .............................................. 36 EUDADATA Pointer...................................... 36–37 Circular Wrapping with EGPDATA Pointer ................. 35 Direct Access.............................................................. 33 General Purpose Buffer ...
Page 164
... ENC424J600/624J600 NOTES: DS39935C-page 162 2010 Microchip Technology Inc. ...
Page 165
... To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. 2010 Microchip Technology Inc. ENC424J600/624J600 CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • ...
Page 166
... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39935C-page 164 Total Pages Sent ________ FAX: (______) _________ - _________ N Literature Number: DS39935C 2010 Microchip Technology Inc. ...
Page 167
... Three-Digit Code or Special Requirements (blank otherwise Engineering Sample 2010 Microchip Technology Inc. ENC424J600/624J600 XXX Examples: Pattern a) ENC424J600-I/ML = Industrial temp., QFN package. b) ENC424J600-I/PT = Industrial temp., 44 leads TQFP package. c) ENC624J600T-I/PT = Industrial temp., 64 leads TQFP package, tape and reel. (1) ; (Industrial) Note tape and reel. DS39935C-page 165 ...
Page 168
... Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 2010 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...