ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 119

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.0
ENC424J600/624J600 devices have multiple interrupt
sources tied to a single output pin, allowing the device
to signal the occurrence of events to the host controller.
The interrupt pin is active-low and is designed for use
by host controllers that can detect falling edges.
Interrupts can also be used on a polling basis without
connecting the interrupt pin. To use interrupts in this
manner, monitor the INT bit (ESTAT<15>) on a periodic
basis.
Interrupts are managed by two registers. The EIE reg-
ister contains the individual interrupt enable bits for
each interrupt driven by the MAC and cryptographic
components. The EIR register holds the individual
interrupt flags. When an interrupt occurs, the
corresponding interrupt flag is set. If the interrupt is
enabled and the INTIE (EIE<15>) global interrupt
enable bit is set, the INT pin is driven low and the INT
flag (ESTAT<15>) becomes set. This logic is shown in
Figure 13-1.
Even when an interrupt is not enabled, its corresponding
interrupt flags are still set when the interrupt condition
occurs. This allows the host controller to poll for certain
lower priority events while using the interrupt pin for
more important tasks.
FIGURE 13-1:
 2010 Microchip Technology Inc.
INTERRUPTS
ENC424J600/624J600 INTERRUPT LOGIC
MODEXIE
MODEXIF
RXABTIE
RXABTIF
PCFULIE
TXABTIF
TXABTIE
PCFULIF
HASHIF
HASHIE
LINKIE
DMAIE
LINKIF
DMAIF
AESIF
AESIE
PKTIE
PKTIF
TXIE
TXIF
EIR/EIE
ENC424J600/624J600
When an enabled interrupt occurs, the INT pin remains
low until all flags causing interrupts are cleared or
masked off (the enable bit is cleared). If more than one
interrupt source is enabled, the host controller must poll
each flag to determine the source(s) of the interrupt. A
good practice is for the host controller to clear the
Global Interrupt Enable bit, INTIE (EIE<15>), immedi-
ately after an interrupt event. This causes the interrupt
pin to return to the non-asserted (high) state. Once the
interrupt has been serviced, the INTIE bit is set again
to re-enable interrupts. If a new interrupt occurs while
servicing another, the act of resetting the global enable
bit will cause a new falling edge to occur on the
interrupt pin and ensure that the host does not miss any
events.
When clearing EIR interrupt flags, it is required that bit-
oriented operations be used. These include Bit Field
Set and Bit Field Clear opcodes for the SPI interface,
and using the Bit Set and Bit Clear registers for the PSP
interfaces. This procedure ensures that interrupts
occurring
inadvertently missed.
INTIE
during the write procedure are
INT
DS39935C-page 117
not