ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 88

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC424J600/624J600
In full duplex, the MAC inhibits transmission of any
packets until the pause timer expires when two
conditions are met:
• Flow control is enabled (RXPAUS bit is set) and
• A valid pause frame was received from the
It will still be possible for software to set the TXRTS bit
to start a transmission. However, this has the effect of
queuing the packet for future transmission instead of
causing an immediate transmission to start. Once the
pause timer expires, the queued packet will transmit
normally, causing any applicable interrupts to occur.
9.2
As Ethernet frames arrive, they are written to the circu-
lar receive buffer, bounded by the Receive Buffer Start
Address (ERXST) register and the end of the physical
memory at 5FFFh. The hardware also maintains a
counter indicating the number of pending frames.
FIGURE 9-3:
DS39935C-page 86
remote node
Initial state, buffer is empty:
Buffer is empty:
Buffer contains pending
data to be processed:
Buffer has wrapped and
contains pending data:
Buffer has wrapped
and is currently full:
01 02
Receiving Packets
H
T
Head Pointer (ERXHEAD)
Tail Pointer (ERXTAIL), skip when reading
Next Packet Pointer for pending frame
EXAMPLES OF RECEIVE BUFFER WRAP BETWEEN ERXHEAD AND ERXTAIL
ERXST
05 06 07 08 0A H
92 93 94 95 96 97 98 99 H T XX 01 02
H
T XX H
T XX 01 02 03 04 05
XX
overwriting data that has not yet been processed.
Each frame starts on an even address. The hardware
maintains a Receive Head Pointer, ERXHEAD, indicating
the next location to be written, and automatically wraps
back to ERXST when it reaches the end of memory. The
Tail Pointer, ERXTAIL, is maintained by software.
Addresses from the Tail Pointer, up to the Head Pointer,
are considered to be protected by software. This allows
the host controller to prevent incoming frames from
When ERXTAIL points to the same location as
ERXHEAD, the receive packet buffer is considered to
be full. Due to this definition, there is no empty condi-
tion. For simplicity, applications may choose to keep
the Tail Pointer always set to two bytes behind the next
frame to be processed, or two bytes behind the Head
Pointer when no frames are pending. Figure 9-3 shows
these pointer relationships.
If ERXHEAD reaches ERXTAIL while receiving a
frame, or if the receive filters reject the packet, the
ERXHEAD Pointer is rolled back to its previous location
and the packet is discarded.
Free byte for incoming data
Byte protected from incoming data
Dummy byte, skip when reading
...
...
...
...
...
8A 8B 8C H
8A 8B 8C 8D 8E 8F 90 91
 2010 Microchip Technology Inc.
T XX 01 02 03 04
T XX
5FFFh