ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 83

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 8-3:
REGISTER 8-4:
 2010 Microchip Technology Inc.
bit 2
bit 1
bit 0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-7
bit 6-0
U-0
U-0
—
—
HFRMEN: Huge Frame Enable bit
1 = Frames of any size will be allowed to be transmitted and received
0 = Frames bigger than MAMXFL will be aborted when transmitted or received
Reserved: Write as ‘ 1 ’
FULDPX: MAC Full-Duplex Enable bit
1 = MAC operates in Full-Duplex mode. For proper operation, the PHY must also be set to Full-Duplex
0 = MAC operates in Half-Duplex mode. For proper operation, the PHY must also be set to Half-Duplex
Unimplemented: Read as ‘ 0 ’
BBIPG<6:0>: Back-to-Back Inter-Packet Gap Delay Time Control bits
When FULDPX (MACON2<0>) = 1 :
Nibble time offset delay between the end of one transmission and the beginning of the next in a
back-to-back sequence. The register value should be programmed to the desired period in nibble times
minus 3. The recommended setting is 15h which represents the minimum IEEE specified Inter-Packet
Gap (IPG) of 0.96  s (at 100 Mb/s) or 9.6  s (at 10 Mb/s).
When FULDPX (MACON2<0>) = 0 :
Nibble time offset delay between the end of one transmission and the beginning of the next in a
back-to-back sequence. The register value should be programmed to the desired period in nibble times
minus 6. The recommended setting is 12h which represents the minimum IEEE specified Inter-Packet
Gap (IPG) of 0.96  s (at 100 Mb/s) or 9.6  s (at 10 Mb/s).
BBIPG6
R/W-0
mode.
mode.
U-0
—
MACON2: MAC CONTROL REGISTER 2 (CONTINUED)
MABBIPG: MAC BACK-TO-BACK INTER-PACKET GAP REGISTER
W = Writable bit
‘1’ = Bit is set
BBIPG5
R/W-0
U-0
—
BBIPG4
R/W-1
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ENC424J600/624J600
BBIPG3
R/W-0
U-0
—
BBIPG2
R/W-0
U-0
—
x = Bit is unknown
BBIPG1
R/W-1
U-0
—
DS39935C-page 81
BBIPG0
R/W-0
U-0
—
bit 8
bit 0