ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 49

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.6.2
The N-byte unbanked SFR instructions are WCRU,
RCRU, BFSU and BFCU. These instructions use an
opcode with a one-byte address argument and do not
depend on the use of BxSEL instructions for SFR bank
selection.
Figure 4-6 shows the timing relationships for these
operations. Like all other opcodes, data is presented on
the SI pin, MSb first. For this class of instructions, the
first byte of data is a specific opcode; the second byte
is the 8-bit absolute address of the target SFR. If the
instruction is a write or bit set/clear opcode, the next
bytes are the data or bit mask to be written. For read
instructions, the next bytes are don’t cares.
For write and bit set/clear instructions, the SO pin is
actively driven with indeterminate ‘1’s or ‘0’s while the
CS pin is driven low. For read instructions, random data
is clocked out on SO during SCK clocks, 1 through 16.
Starting with the 17th clock, data is clocked out
FIGURE 4-6:
 2010 Microchip Technology Inc.
SCK
SCK
Write Operation
Read Operation
SO
SO
CS
CS
SI
SI
UNBANKED SFR OPERATIONS
Hi-Z
Hi-Z
x
x
1
1
0
0
N-BYTE SPI OPCODE (UNBANKED SFR OPERATIONS)
2
0
2
0
x
x
3
1
x
3
1
x
Opcode
Opcode
4
0
4
0
x
x
5
x
5
0 c2
x
0 c2
6
6
x
x
c1 0
c1 0
7
x
7
x
8
8
x
x
a7
a7
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
x
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
x
Unbanked SFR Address
Unbanked SFR Address
a6
a6
x
x
a5 a4 a3 a2 a1 a0
a5 a4 a3 a2 a1 a0
x
x
x
x
ENC424J600/624J600
x
x
byte-wise on SO, MSb first. As with three-byte
instructions, the lower byte of a data word is presented
first, followed by the upper byte.
As long as the CS pin is held low, the instruction
continues to execute, automatically incrementing to the
next register address in the SFR space and writing data
from SI to, or outputting data on SO from, subsequent
registers. When the end of a bank is reached, the
address continues to the top of the next bank.
Addresses continue to increment through the banks
into the unbanked SFR area (addresses 80h through
9Fh), then wrap around to the start of Bank 0 (00h). The
SFR bank value used by the BxSEL and RBSEL
opcodes is not affected by the execution of unbanked
SFR instructions.
There are four unbanked SFR opcodes, summarized in
Table 4-5. Except for addressing, the unbanked SFR
instructions are analogous to the banked SFR instruc-
tions. However, there are certain differences in their
behavior with certain pointer registers, as noted below.
x
x
x
x
x
x
d7 d6 d5 d4 d3 d2 d1
d7 d6 d5 d4 d3 d2 d1 d0
x
x
Write 1st Byte
Read 1st Byte
x
x
x
x
x
DS39935C-page 47
d0
x
25 26 27
D7 D6 D5
25 26 27
D7 D6 D5
x
Additional
Additional
x
x