ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 85

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.0
Beyond providing the transceiver interface to the
network medium, ENC424J600/624J600 devices also
handle many of the mechanical tasks of packet
management, off-loading much of the routine Ethernet
housekeeping from the host application. The device
manages the separate transmit and receive buffers,
handles transmission and potential collisions, filters
incoming packets, and stores received packets with the
additional information required for processing. The
host controller writes data to the memory, configures
the length of the packet to send, initiates the transmis-
sions and reads incoming packets from the receive
buffer. Padding and checksum generation, as well as
status information on received packets, are all handled
automatically.
9.1
The general purpose buffer is bounded by the begin-
ning of the address space (0000h) and the last byte
before the beginning of the receive buffer (ERXST – 1).
Since ERXST must be word-aligned, both buffers start
on even addresses and end on odd addresses. For
details on buffer allocation, see Section 3.5 “SRAM
Buffer” .
The packet to be transmitted is defined by two values:
the Transmit Data Start Pointer, ETXST, and the
Transmit Buffer Length Pointer, ETXLEN. When trans-
mitting a packet, the device reads the ETXLEN bytes,
beginning at the address indicated by ETXST. If the end
of the general purpose buffer is encountered during this
process, the operation will wrap around to the beginning
of the general purpose buffer space (0000h). Packets
can also be transmitted directly from the receive buffer
(for instance, when changing the source and destination
addresses). If the end of the receive buffer is
encountered, the operation wraps to the beginning of the
receive buffer instead. This wrap-around behavior
precludes packets from spanning both buffers.
Figure 9-1 shows three examples of the wrapping
behavior. Packet 1 in the diagram is transmitted without
any wrapping. Packet 2 reaches the end of the general
purpose buffer, and therefore, wraps to address 0000h.
Packet 3 is being transmitted from the receive buffer,
and therefore, wraps to ERXST when the end of the
receive buffer is reached.
The device can be configured to insert the source MAC
address using the values from the MAADR registers.
This feature is enabled by setting the TXMAC bit
(ECON2<13>). When enabled, the device reads the
6-byte destination address from memory, inserts the
6-byte source MAC address from the MAADR registers
into the transmitted byte stream, then continues reading
and transmitting the remaining bytes from memory.
 2010 Microchip Technology Inc.
TRANSMITTING AND
RECEIVING PACKETS
Transmitting Packets
ENC424J600/624J600
FIGURE 9-1:
The value of ETXLEN only indicates the number of
bytes to read from memory, not the number of bytes to
be transmitted. If the device is configured to insert the
source MAC address, add padding or append the CRC;
the actual number of bytes transmitted on the physical
medium will increase. Figure 9-2 shows how to
configure ETXLEN for three identical packets of data
when various transmission options are configured.
Before transmitting any packets, the device needs to
be initialized (see Section 8.0 “Initialization” ). Setting
TXRTS (ECON1<1>) initiates the transmission. This bit
is automatically cleared by hardware when the opera-
tion is complete. In addition, the device can also be
configured to assert the TXIF interrupt and the external
interrupt signal on completion (see Section 13.0
“Interrupts” for additional details).
Transmission operations can be aborted by manually
clearing the TXRTS bit at any time. If a packet transmis-
sion is in progress, it will be aborted immediately and the
device will send a jam signal, effectively notifying the link
partner to discard any partial packet it has received.
ERXST
5FFFh
0000h
Example
Packet
1
2
3
Packet 2
Packet 1
Packet 2
Packet 3
Packet 3
(cont.)
(cont.)
EXAMPLES OF TX
BUFFER WRAPPING
ETXST
5F00h
4200h
4600h
4200h
4800h
4900h
5F00h
0100h
4600h
DS39935C-page 83
ETXLEN
1024
768
512
General
Purpose
Buffer
Receive
Buffer