ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 51

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.6.3
The six N-byte SRAM instructions function in a similar
manner to the banked SFR instructions, in that they use
a single byte opcode to define the operation and target
register. In terms of timing, they are virtually identical, as
shown in Figure 4-7.
Like all other opcodes, data is presented on the SI pin,
MSb first. For all instructions, the first byte of data is the
opcode. If the instruction is a write opcode, the next
bytes are the data to be written. For read instructions,
the next bytes are don’t cares.
For write instructions, the SO pin is actively driven with
indeterminate ‘1’s or ‘0’s while the CS pin is driven low.
For read instructions, random data is clocked out on
FIGURE 4-7:
 2010 Microchip Technology Inc.
Write Operation
Read Operation
SCK
SCK
CS
SO
CS
SO
SI
SI
SRAM BUFFER OPERATIONS
Hi-Z
Hi-Z
x
x
1
1
0
0
N-BYTE SPI OPCODE (SRAM BUFFER OPERATIONS)
2
2
0
x
0
x
3
3
1
x
1
x
Opcode
Opcode
c4 c3 c2
c4 c3 c2
4
x
4
x
5
5
x
x
6
6
x
x
7
7
1
x
0
x
8
x
8
0
x
0
d7
d7 d6 d5 d4 d3 d2 d1 d0
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
x
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
d6
x
d5 d4 d3 d2 d1
Read 1st Byte
Write 1st Byte
x
x
ENC424J600/624J600
x
SO during SCK clocks, 1 through 8. Starting with the
9th clock, data is clocked out byte-wise on SO, MSb
first.
As long as the CS pin is held low, the instruction
continues to execute, automatically incrementing to the
next SRAM address according to the pointer wrapping
rules described in Section 3.5.5 “Indirect SRAM Buffer
Access”. The associated read or write pointer SFRs are
automatically updated for each 8 SCK clocks. To
terminate the read or write operation, the CS signal must
be returned high.
There are 6 instructions divided equally between read
and write instructions. They are summarized in
Table 4-6.
x
x
d0
x
D7 D6 D5 D4 D3 D2 D1
D7 D6 D5
x
x
Read 2nd Byte
Write 2nd Byte
x
(optional)
(optional)
D4 D3 D2 D1 D0
x
x
x
x
DS39935C-page 49
D0
x
25 26 27
D7 D6 D5
25 26 27
D7 D6 D5
x
Additional
Additional
x
x