ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 32

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC424J600/624J600
REGISTER 3-2:
REGISTER 3-3:
DS39935C-page 30
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-2
bit 1
bit 0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-4
bit 3
bit 2
bit 1
bit 0
U-0
U-0
U-0
U-0
—
—
—
—
Unimplemented: Read as ‘0’
MIISCAN: MII Scan Enable bit
1 = PHY register designated by MIREGADR<4:0> is continuously read and the data is copied to MIRD
0 = No MII Management scan operation is in progress
MIIRD: MII Read Enable bit
1 = PHY register designated by MIREGADR<4:0> is read once and the data is copied to MIRD
0 = No MII Management read operation is in progress
Unimplemented: Read as ‘0’
Reserved: Ignore on read
NVALID: MII Management Read Data Not Valid Status bit
1 = The contents of MIRD are not valid yet
0 = The MII Management read cycle has completed and MIRD has been updated
SCAN: MII Management Scan Status bit
1 = MII Management scan operation is in progress
0 = No MII Management scan operation is in progress
BUSY: MII Management Busy Status bit
1 = A PHY register is currently being read or written to
0 = The MII Management interface is Idle
U-0
U-0
U-0
U-0
—
—
—
—
MICMD: MII MANAGEMENT COMMAND REGISTER
MISTAT: MII MANAGEMENT STATUS REGISTER
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
U-0
R-0
—
—
—
r
NVALID
U-0
U-0
U-0
R-0
—
—
—
 2010 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
MIISCAN
R/W-0
SCAN
U-0
U-0
R-0
—
—
R/W-0
MIIRD
BUSY
U-0
U-0
R-0
—
—
bit 8
bit 0
bit 8
bit 0