ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 55

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.2.5
When using a 16-bit data bus width, all registers and
direct access to SRAM can be accomplished through
16-bit accesses. Therefore, these modes are poten-
tially twice as fast as their 8-bit equivalent parallel
mode.
hardware-managed
EGPDATA, ERXDATA and EUDADATA, are always
8-bit regardless of the interface used. Therefore, in
many applications, it will not be practically feasible to
transfer 16 bits of meaningful data for all bus transfer
cycles.
When reading from the EGPDATA, ERXDATA and
EUDADATA registers on an interface with a multi-
plexed address bus, it is possible to latch the address
only once and then perform back-to-back reads or
writes without performing additional address latch
cycles. This can provide a significant performance
improvement when sequentially reading or writing an
array of data to/from the RAM. Due to this benefit, 8-Bit
Multiplexed modes (Modes 5 and 6) approach the
theoretical performance of the Demultiplexed PSP
Modes 1 and 2.
5.3
The eight PSP modes are selected using the PSPCFG
pins. The address/data bus and port control connec-
tions
significantly, as do the timing relationships between
address/data and control signals. Each of the modes is
described in detail in the following sections.
 2010 Microchip Technology Inc.
differ
PSP Modes
However,
PERFORMANCE
CONSIDERATIONS
between
SRAM
accesses
the
read/write
modes,
through
sometimes
registers,
the
ENC424J600/624J600
5.3.1
PSP Mode 1 is an 8-bit, fully demultiplexed mode that
is available on 64-pin devices only. The parallel inter-
face consists of 8 bi-directional data pins (AD<7:0>)
and 9 to 15 separate address pins (A<14:0>). To select
PSP Mode 1, tie PSPCFG2, PSPCFG3 and PSPCFG4
to V
This mode uses active-high Read and Write strobes
(RD and WR) in conjunction with a Chip Select (CS)
signal. These three pins allow the host to select the
device, then signal when a read operation is desired or
when valid data is being presented to be written. The
AD<7:0> pins stay in a high-impedance state any time
CS or RD is low.
To perform a read operation:
1.
2.
3.
When RD is raised high, the data bus begins to drive
out indeterminate data for a brief period, then switches
to the correct read data after the appropriate read
access time has elapsed. When the RD strobe is
lowered, AD<7:0> return to a high-impedance state.
To perform a write operation:
1.
2.
3.
4.
For proper operation, do not raise RD and WR
Sample timing diagrams for reading and writing data in
this mode are provided in Figure 5-2 and Figure 5-3,
respectively.
simultaneously while the ENCX24J600 is selected.
SS
Raise the CS line (if connected to the host).
Present the address to be read onto the address
bus.
Raise the RD strobe and wait the required time
for the access to occur.
Raise the CS line (if connected to the host).
Present the address onto the address bus.
Present the data on the data bus.
Strobe the WR signal high and then low.
. Figure 5-1 shows the connections required.
MODE 1
DS39935C-page 53