ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 20

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC424J600/624J600
3.1.2
When one of the parallel interfaces is selected, the
memory map is very different from the SPI map. There
are two different memory address spaces (Figure 3-2):
• the main memory area
• the PHY register area
As in the serial memory map, the main memory area is
a linear, byte-addressable space of 32 Kbytes, with the
SRAM buffer located in the first 24-Kbyte region. The
cryptographic data memory is also mapped to the same
location as in the serial memory map. The main differ-
ence is that the SFRs are now located to an area with a
higher address than the cryptographic data space. Addi-
tional memory areas above the SFRs are reserved for
their accompanying Bit Set and Bit Clear registers.
Except for the cryptographic data memory, all
addresses in the main memory area are directly
accessible using the PSP bus. As with the serial inter-
face, the cryptographic memory can only be accessed
through the DMA.
FIGURE 3-2:
DS39935C-page 18
Note 1:
Main Area
PHY Register Area
SFR Bit Clear Registers
PSP Address Bus and
SFR Bit Set Registers
Cryptographic Data
(DMA access only)
Special Function
Registers (R/W)
2:
Unimplemented
Unimplemented
SRAM Buffer
PSP INTERFACE MAPS
8-Bit PSP
Memory areas not shown to scale.
Addresses in this range are accessible only through internal address pointers of the DMA module.
16-Bit, MIIM Access Only
All Pointers
ENC424J600/624J600 MEMORY MAPS FOR PSP INTERFACES
5FFFh
7C4Fh
7E9Fh
7FFFh
7E00h
7F00h
7F7Fh
7F80h
0000h
7800h
(2)
MIREGADR
(2)
1Fh
00h
Main Area
PHY Register Area
The difference between the 8-bit and 16-bit interfaces is
buffer as a byte-wide, byte-addressable space.
how the SRAM buffer is addressed by the external
address bus. In 16-bit data modes, the address bus
treats the buffer as a 16-byte wide, word-addressable
space, spanning 000h to 3FFFh. In 8-bit data modes, the
address bus treats the buffer as an 8-bit, byte-address-
able space, ranging from 0000h to 7FFFh. In either case,
the SFRs used as memory pointers still address the
The PHY SFR space is implemented in the same
manner as the SPI interface described above.
In both 8-bit and 16-bit PSP modes, full device func-
tionality can be realized without using the full width of
the address bus. This is because the SRAM buffer can
still be read and written to by using SFR pointers. In
practical terms, this can allow designers in space or pin
constrained applications to only connect a subset of the
A or AD address pins to the host microcontroller. For
example, in the 8-Bit Multiplexed PSP Modes 5 or 6,
tying pins, AD<14:9> to V
access to all SFRs. This reduces the number of pins
required for connection to the host controller, including
the interface control pins to 12 or 13.
PSP Address Bus (Word Address)
Special Function Registers (R/W)
16-Bit, MIIM Access Only
SFR Bit Clear Registers
Pointers (Byte Address)
SFR Bit Set Registers
Cryptographic Data
(DMA access only)
Unimplemented
Unimplemented
SRAM Buffer
16-Bit PSP
 2010 Microchip Technology Inc.
DD
, still allows direct address
MIREGADR
(1)
7C4Fh
7800h
5FFFh
0000h
(2)
(2)
0000h
2FFFh
3F00h
3F4Fh
3F80h
3FBFh
3FC0h
3FFFh
00h
1Fh