ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 50

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

raising CS.
ENC424J600/624J600
4.6.2.1
The Write Control Register Unbanked (WCRU) opcode
starts with the opcode, ‘00100010’ (22h), followed by
the unbanked SFR register address during SPI clocks,
9 through 16. For example, to write to ECON2L at
address 6Eh, the instruction would be ‘22h 6Eh’,
followed by the data to be written.
When the host controller is finished writing data, it should
raise the CS line, putting the device in an inactive state
and preparing it for the next SPI instruction. When finish-
ing a WCRU transaction, ensure that adequate CS hold
time is provided for the last write to complete before
Generally, WCRU can be executed on most register
addresses, in any sequence and for any length. An
important exception is when WCRU is used on any MAC
or MII register. These registers must be written as
whole 16-bit registers, low byte first (e.g., MACON1
must be written by first writing to MACON1L, then
MACON1H). Writing only to the upper byte of a MAC or
MII register results in a successful write to the upper
register, while the lower register is written with indeter-
minate data. If a WCRU instruction is aborted by raising
CS while writing to the upper byte of a MAC or MII
register, neither the upper nor lower byte will be
updated.
In addition, WCRU cannot be used to write to the SRAM
buffer virtual data windows (EGPDATA, ERXDATA and
EUDADATA). Writing to the buffer address indicated by
the corresponding address pointers’ attempts has no
effect on the memory location, and the pointers do not
auto-increment. To write to the SRAM buffer using the
virtual data windows, always use the SRAM buffer
opcodes
instead.
4.6.2.2
The Read Control Register Unbanked (RCRU) opcode
starts with the opcode, ‘00100000’ (20h), followed by
the unbanked SFR register address during SPI clocks,
9 through 16. Continuing the previous example, to read
ECON2L at address 6Eh, the complete two-byte
instruction would be ‘20h 6Eh’.
TABLE 4-5:
DS39935C-page 48
Read Control Register(s), Unbanked
Write Control Register(s), Unbanked
Bit Field(s) Set, Unbanked
Bit Field(s) Clear, Unbanked
Legend: x/X = read data (LSB/MSB), d/D = write data (LSB/MSB), A = unbanked SFR address. ‘X’ and ‘D’ are optional.
(WGPDATA,
WCRU Opcode
RCRU Opcode
Instruction
N-BYTE UNBANKED SFR INSTRUCTIONS
WRXDATA
and
WUDADATA)
Mnemonic
RCRU
WCRU
BFSU
BFCU
0010 0000
0010 0010
0010 0100
0010 0110
1st Byte
Opcode
Read operations can be performed on most register
addresses, in any sequence and for any length.
However, due to volatile register shadowing, it is
recommended
register pair be read in sequence (low byte first) to
obtain the correct value. See Section 9.2 “Receiving
Packets” for additional information.
Similar to WCRU, RCRU cannot be used to read data
from the SRAM buffer using the virtual data windows.
Reading the buffer address indicated by the corre-
sponding address pointers returns indeterminant data
and the pointers do not auto-increment. To read from
the buffer using the virtual data windows, always use
the SRAM buffer opcodes (RGPDATA, RRXDATA and
RUDADATA) instead.
4.6.2.3
The Bit Field Set Unbanked (BFSU) and Bit Filed Clear
Unbanked (BFCU) opcodes start with the opcode,
‘00100100’ (24h) for BFSU, or ‘00100110’ (26h) for
BFCU, followed by the unbanked SFR register address
during SPI clocks, 9 through 16. In terms of timing and
automatic address increment, they behave almost
identically to the WCRU opcode.
BFSU and BFCU function in the same manner as BFS
and BFC, by setting or clearing individual bits in the tar-
get register through the use of a bit mask. They are also
used in the same situations as BFS and BFC; namely,
when it is necessary to manipulate a single control bit
or interrupt flag in a dynamic situation, while avoiding
the disruption of other bits. See Section 4.6.1.3 “BFS
and BFC Opcodes” for a detailed explanation.
Note 1: Unlike WCRU, BFSU and BFCU cannot be
2: BFSU and BFCU opcodes have no effect
AAAA AAAA
AAAA AAAA
AAAA AAAA
AAAA AAAA
2nd Byte
used to modify MAC or MII registers.
Never use these opcodes on MAC and
MII registers.
on any SFR in the unbanked region
(addresses 80h through 9Fh).
BFSU and BFCU Opcodes
that
the
 2010 Microchip Technology Inc.
xxxx xxxx
dddd dddd
dddd dddd
dddd dddd
Argument
3rd Byte
ERXHEADH:ERXHEADL
XXXX XXXX
DDDD DDDD
DDDD DDDD
DDDD DDDD
Nth Byte