SGTL5000XNLA3R2 Freescale Semiconductor, SGTL5000XNLA3R2 Datasheet - Page 71

• Manufacturer Part Number: SGTL5000XNLA3R2
• Description: IC AUDIO CODEC STEREO 20-QFN
• Manufacturer: Freescale Semiconductor
• Type: Stereo Audior

Specifications of SGTL5000XNLA3R2

• Data Interface: I²C, Serial, SPI™
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 90 / 100
• Voltage - Supply, Analog: 1.62 V ~ 3.6 V
• Voltage - Supply, Digital: 1.1 V ~ 2 V, 1.62 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-UFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SGTL5000 EA2 DS-0-3
BITS
BITS
15
15
14
13
12
10
11
0
9
8
7
6
5
4
3
2
1
LINEOUT_TO_VD
INVERT_DAC_SA
INVERT_ADC_SA
MONOMODE_DA
VCO_TUNE_AGA
14
DAC_EXTEND_R
LO_PASS_MAST
INVERT_DAC_D
DAC_DOUBLE_I
INVERT_ADC_D
MPLE_CLOCK
DAC_DIS_RTZ
MPLE_CLOCK
DAC_CLASSA
ATA_TIMING
ATA_TIMING
TESTMODE
ADC_LESSI
7.0.0.22. CHIP_ANA_TEST2
ERVAG
FIELD
FIELD
SPARE
RSVD
13
DA
TZ
IN
C
12
RW RESET
RW RESET
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
11
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
10
Enable the analog testmode paths
9
Reserved
Changes the lineout amplifier power supply from VDDIO to
VDDA. Typically lineout should be on the higher power
supply. This bit is useful when VDDA is ~3.3V and VDDIO is
~1.8V.
Spare registers to analog.
Copy the left channel DAC data to the right channel. This
allows both left and right to play from MONO dac data.
When toggled high then low forces the PLL VCO to retune the
number of inverters in the ring oscillator loop.
Tie the main analog VAG to the lineout VAG. This can improve
SNR for the lineout when both are the same voltage.
Change the clock edge used for the DAC output sampling.
Change the clock edge used for the digital to analog DAC data
crossing.
Extend the return-to-zero time for the DAC.
Double the output current of the DAC amplifier when it is in
classA mode.
Turn off the return-to-zero in the DAC. In mode cases this will
hurt the SNDR of the DAC.
Turn off the classAB mode in the DAC amplifier. This mode
should normally not be used. The output current will not be
high enough to support a full scale signal in this mode.
Change the clock edge used for the ADC sampling.
Change the clock edge used for the analog to digital ADC data
crossing
Drops ADC bias currents by 20%
8
7
0x003A
6
DEFINITION
DEFINITION
5
4
3
2
SGTL5000
1
0
71