SGTL5000XNLA3R2 Freescale Semiconductor, SGTL5000XNLA3R2 Datasheet - Page 34

• Manufacturer Part Number: SGTL5000XNLA3R2
• Description: IC AUDIO CODEC STEREO 20-QFN
• Manufacturer: Freescale Semiconductor
• Type: Stereo Audior

Specifications of SGTL5000XNLA3R2

• Data Interface: I²C, Serial, SPI™
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 90 / 100
• Voltage - Supply, Analog: 1.62 V ~ 3.6 V
• Voltage - Supply, Digital: 1.1 V ~ 2 V, 1.62 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-UFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SGTL5000
34
(SCLKFREQ = 0; SCLK_INV = 0; DLEN = 1; I2S_MODE = 0; LRALIGN = 0; LRPOL = 0)
(SCLKFREQ = 0; SCLK_INV = 0; DLEN = 1; I2S_MODE = 0; LRALIGN = 1; LRPOL = 0)
SCLKFREQ = 0; SCLK_INV = 0; DLEN = 1; I2S_MODE = 1; LRALIGN = 1; LRPOL = 0)
I2S_DIN, DOUT
I2S_DIN, DOUT
I2S_DIN, DOUT
I2S_LRCLK
I2S_LRCLK
I2S_LRCLK
I2S_SCLK
I2S_SCLK
I2S_SCLK
Right Justified Format (n = bit length)
Left Justified Format (n = bit length)
5.8.2.
L
n
L
I2S Format (n = bit length)
(n-1)
L
PCM Mode
The I2S port can also be configured into a PCM mode (also known as DSP mode).
This mode is provided to allow connectivity to to external devices such as Bluetooth
modules. PCM mode differs from other interface formats presented in section 5.8.1
in that the frame clock (I2S_LRCLK) does not represent a different channel when
high or low, but is a bit-wide pulse that marks the start of a frame. Data is aligned
such that the left channel data is immediately followed by right channel data. Zero
padding is filled in for the remaining bits. The data and frame clock may be config-
ured to clock in on the rising or falling edge of Bit Clock.
n
L
(n-1)
Figure 12. I2S Port Supported Formats
CHIP_I2S0_CTRL field values:
CHIP_I2S0_CTRL field values:
CHIP_I2S0_CTRL field values:
L
n
L
L01
L
(n-1)
1
L00
L
0
L
0
R
n
R
R
(n-1)
n
R
( n-1)
R
n
R
R01
R
(n-1)
1
R00
SGTL5000 EA2 DS-0-3
R
0
R0
L
n
L
(n-1)
L
n