SGTL5000XNLA3R2 Freescale Semiconductor, SGTL5000XNLA3R2 Datasheet - Page 68

• Manufacturer Part Number: SGTL5000XNLA3R2
• Description: IC AUDIO CODEC STEREO 20-QFN
• Manufacturer: Freescale Semiconductor
• Type: Stereo Audior

Specifications of SGTL5000XNLA3R2

• Data Interface: I²C, Serial, SPI™
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 90 / 100
• Voltage - Supply, Analog: 1.62 V ~ 3.6 V
• Voltage - Supply, Digital: 1.1 V ~ 2 V, 1.62 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-UFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SGTL5000
68
BITS
BITS
15:11
10:0
15
1
0
LINEOUT_POWE
14
ADC_POWERUP
FRAC_DIVISOR
INT_DIVISOR
7.0.0.18. CHIP_PLL_CTRL
This register may only be changed after reset, and before PLL_POWERUP is set.
FIELD
FIELD
RUP
13
12
RW RESET
RW RESET
RW
RW
RW
RW
11
0x0
0x0
0xA
0x0
10
Power up the ADCs
0x0 = Power down
0x1 = Power up
Power up the lineout amplifiers
0x0 = Power down
0x1 = Power up
9
This is the integer portion of the PLL divisor. To determine the
value of this field, use the following calculation:
INT_DIVISOR = FLOOR(PLL_OUTPUT_FREQ/
INPUT_FREQ)
PLL_OUTPUT_FREQ = 180.6336 MHz if System sample rate
= 44.1 KHz
else
PLL_OUTPUT_FREQ = 196.608 MHz if System sample rate
!= 44.1 KHz
INPUT_FREQ = Frequency of the external MCLK provided if
CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0x0
else
INPUT_FREQ = (Frequency of the external MCLK provided/2)
If CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0x1
This is the fractional portion of the PLL divisor. To determine
the value of this field, use the following calculation:
FRAC_DIVISOR = ((PLL_OUTPUT_FREQ/INPUT_FREQ) -
INT_DIVISOR)*2048
PLL_OUTPUT_FREQ = 180.6336 MHz if System sample rate
= 44.1 KHz
else
PLL_OUTPUT_FREQ = 196.608 MHz if System sample rate
!= 44.1 KHz
INPUT_FREQ = Frequency of the external MCLK provided if
CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0x0
else
INPUT_FREQ = (Frequency of the external MCLK provided/2)
If CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0x1
8
7
0x0032
6
DEFINITION
DEFINITION
5
4
SGTL5000 EA2 DS-0-3
3
2
1
0