SGTL5000XNLA3R2 Freescale Semiconductor, SGTL5000XNLA3R2 Datasheet - Page 69

• Manufacturer Part Number: SGTL5000XNLA3R2
• Description: IC AUDIO CODEC STEREO 20-QFN
• Manufacturer: Freescale Semiconductor
• Type: Stereo Audior

Specifications of SGTL5000XNLA3R2

• Data Interface: I²C, Serial, SPI™
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 90 / 100
• Voltage - Supply, Analog: 1.62 V ~ 3.6 V
• Voltage - Supply, Digital: 1.1 V ~ 2 V, 1.62 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-UFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SGTL5000 EA2 DS-0-3
BITS
BITS
15:12
15:10
10:4
15
15
2:0
7:5
11
3
9
8
ENABLE_INT_OS
14
INPUT_FREQ_DI
14
LRSHORT_STS
CSHORT_STS
RESERVED
7.0.0.19. CHIP_CLK_TOP_CTRL
Miscellaneous controls for the clock block.
7.0.0.20. CHIP_ANA_STATUS
Status bits for analog blocks.
FIELD
FIELD
RSVD
RSVD
RSVD
RSVD
13
13
V2
C
12
12
RW RESET
RW RESET
RW
RW
RW
RW
RO
RO
RO
RO
RO
11
11
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
10
10
9
Reserved
Setting this bit enables an internal oscillator to be used for the
zero cross detectors, the short detect recovery, and the
charge pump. This will allow the I2S clock to be shut off while
still operating an analog signal path. This bit can be kept on
when the I2S clock is enabled, but the I2S clock is more
accurate so it is preferred to clear this bit when I2S is present.
Reserved
SYS_MCLK divider before PLL input
0x0 = pass through
0x1 = SYS_MCLK is divided by 2 before entering PLL
This must be set when the input clock is above 17Mhz. This
has no effect when the PLL is powered down.
Reserved
9
Reserved
This bit is high whenever a short is detected on the left or right
channel headphone drivers.
0x0 = Normal
0x1 = Short detected
This bit is high whenever a short is detected on the capless
headphone common/center channel driver.
0x0 = Normal
0x1 = Short detected
Reserved
8
8
7
7
0x0036
6
6
0x0034
DEFINITION
DEFINITION
5
5
4
4
3
3
2
2
SGTL5000
1
1
0
0
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