SGTL5000XNLA3R2 Freescale Semiconductor, SGTL5000XNLA3R2 Datasheet - Page 43

• Manufacturer Part Number: SGTL5000XNLA3R2
• Description: IC AUDIO CODEC STEREO 20-QFN
• Manufacturer: Freescale Semiconductor
• Type: Stereo Audior

Specifications of SGTL5000XNLA3R2

• Data Interface: I²C, Serial, SPI™
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 90 / 100
• Voltage - Supply, Analog: 1.62 V ~ 3.6 V
• Voltage - Supply, Digital: 1.1 V ~ 2 V, 1.62 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-UFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SGTL5000 EA2 DS-0-3
SS
SCK
MOSI
Addr
15
31
5.10.2. SPI
S
Addr
S
S
14
S
Address
Device
Address
Address
Device
Device
Address
Device
Serial Peripheral Interface (SPI) is a communications protocol supported by the
SGTL5000. The SGTL5000 is always a slave. The CTRL_AD0_CS is used as the
slave select (SS) when the master wants to select the SGTL5000 for communica-
tion. CTRL_CLK is connected to master’s SCLK and CTRL_DATA is connected to
master’s MOSI line. The part only supports allows SPI write operations and does
not support read operations.
Figure 20 below shows the functional timing diagram of the SPI communication pro-
tocol as supported by SGTL5000 chip. Note that on the rising edge of the SS, the
chip latches to previous 32 bits of data. It interprets the latest 16-bits as register
value and 16-bits preceding it as register address.
(0)
Addr
W
8
16-bits Register Address
Figure 20. Functional Timing Diagram of SPI Protocol
(0)
(0)
W
W
A
ADDR
byte 1
start
A
A
Table 17. Read Continuing Auto increment
R
Addr
7
23
ADDR
byte 1
ADDR
byte 1
start
Addr
A
A
Table 15. Read Single Location
6
Table 14. Write Auto increment
Table 16. Read Auto increment
ADDR
byte 0
start
A
byte 1
DATA
A
[n+2]
A Sr
ADDR
byte 0
ADDR
byte 0
start
Addr
0
Address
A
Device
A
A
Val
15
byte 0
15
Sr
byte 1
DATA
DATA
[n+2]
[n]
(1)
Val
R
14
Address
Device
A DATA
A
byte 1
A
[n]
byte 0
DATA
[n]
Val
8
(1)
R
A DATA
byte 1
DATA
[n+3]
16-bits Register Value
byte 0
A
A
[n]
Val
byte 1
byte 1
DATA
DATA
[n+1]
7
7
A DATA
A
Val
6
byte 1
[n+1]
On rising edge of SS, latch
the last 32 bits of data
A
A
byte 0
DATA
[n+3]
SGTL5000
A DATA
byte 0
byte 0
DATA
DATA
[n+1]
byte 0
[n+1]
Val
0
0
N
N
A
N P
P
P
43
P