SGTL5000XNLA3R2 Freescale Semiconductor, SGTL5000XNLA3R2 Datasheet - Page 55

• Manufacturer Part Number: SGTL5000XNLA3R2
• Description: IC AUDIO CODEC STEREO 20-QFN
• Manufacturer: Freescale Semiconductor
• Type: Stereo Audior

Specifications of SGTL5000XNLA3R2

• Data Interface: I²C, Serial, SPI™
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 90 / 100
• Voltage - Supply, Analog: 1.62 V ~ 3.6 V
• Voltage - Supply, Digital: 1.1 V ~ 2 V, 1.62 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-UFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SGTL5000 EA2 DS-0-3
BITS
BITS
15:6
15:9
15
15
5:4
3:2
1:0
14
14
RATE_MODE
MCLK_FREQ
7.0.0.3.
7.0.0.4.
SYS_FS
FIELD
FIELD
RSVD
RSVD
13
13
12
12
CHIP_CLK_CTRL
CHIP_I2S_CTRL
RW RESET
RW RESET
RW
RW
RW
RO
RO
11
11
0x0
0x0
0x2
0x0
0x0
10
10
9
Reserved
Sets the sample rate mode. MCLK_FREQ is still specified
relative to the rate in SYS_FS
0x0 = SYS_FS specifies the rate
0x1 = Rate is 1/2 of the SYS_FS rate
0x2 = Rate is 1/4 of the SYS_FS rate
0x3 = Rate is 1/6 of the SYS_FS rate
Sets the internal system sample rate
0x0 = 32 kHz
0x1 = 44.1 kHz
0x2 = 48 kHz
0x3 = 96 kHz
Identifies incoming SYS_MCLK frequency and if the PLL
should be used
0x0 = 256*Fs
0x1 = 384*Fs
0x2 = 512*Fs
0x3 = Use PLL
The 0x3 (Use PLL) setting must be used if the SYS_MCLK is
not a standard multiple of Fs (256, 384 or 512). This setting
can also be used if SYS_MCLK is a standard multiple of Fs.
Before this field is set to 0x3 (Use PLL), the PLL must be
powered up by setting CHIP_ANA_POWER-
>PLL_POWERUP and CHIP_ANA_POWER-
>VCOAMP_POWERUP. Also, the PLL dividers must be
calculated based on the external MCLK rate and
CHIP_PLL_CTRL register must be set (see CHIP_PLL_CTRL
register description details on how to calculate the divisors).
9
Reserved
8
8
7
7
0x0006
0x0004
6
6
DEFINITION
DEFINITION
5
5
4
4
3
3
2
2
SGTL5000
1
1
0
0
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