SGTL5000XNLA3R2 Freescale Semiconductor, SGTL5000XNLA3R2 Datasheet
SGTL5000XNLA3R2
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SGTL5000XNLA3R2 Summary of contents
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Low Power Stereo Codec with Headphone Amp DESCRIPTION The Low Power Stereo Codec with Headphone Amp from Freescale is designed to provide a complete audio solution for portable products needing line-in, mic-in, line-out, headphone-out, and digital I/O. Deriving it’s architecture ...
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SGTL5000 Package 3mm x 3mm 20 pin QFN 5mm x 5mm 32 pin QFN Freescale, Inc. makes no warranty for the use of its products, assumes no responsibility for any errors which may appear in this document, and makes no ...
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ELECTRICAL SPECIFICATIONS 1.1. Absolute Maximum Ratings Exceeding the absolute maximum ratings shown in Table 1 could cause permanent damage to SGTL5000 and is not recommended. Normal operation is not guaran- teed at the absolute maximum ratings and extended exposure ...
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SGTL5000 Test Conditions unless otherwise noted: VDDIO=1.8V, VDDA = 1.8V, Ta=25C, Slave mode 48kHz, MCLK = 256Fs, 24 bit input. Parameter THD+N Frequency Response Channel Separation Line In -> Headphone_Lineout (CODEC Bypass Mode) (-60dB input) SNR THD+N (10k ...
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Test Conditions unless otherwise noted: VDDIO=3.3V, VDDA =3.3V, Ta=25C, Slave mode 48kHz, MCLK = 256Fs, 24 bit input. ADC tests were conducted with refbias = -37.5%, all other tests conducted with refbias = -50% Parameter Line In Input ...
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SGTL5000 Test Conditions unless otherwise noted: VDDIO=3.3V, VDDA =3.3V, Ta=25C, Slave mode 48kHz, MCLK = 256Fs, 24 bit input. ADC tests were conducted with refbias = -37.5%, all other tests conducted with refbias = -50% Parameter (-60dB input) ...
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I2C This section provides timing for the SGTL5000 while in I2C mode (CTRL_MODE = =0). Symbol Parameter Fi2c_clk I2C Serial Clock Frequency Ti2csh I2C Start condition hold time Ti2cstsu I2C Stop condition setup time Ti2cdsu I2C Data input setup ...
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SGTL5000 Symbol Parameter Tspidh SPI data input hold time Tspiclkl SPI CTRL_CLK low time Tspiclkh SPI CTRL_CLK high time Tccs SPI clock to chip select Tcsc SPI chip select to clock Tcsl SPI chip select low Tcsh SPI chip select ...
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Symbol Parameter Ti2s_h I2S hold time . I2S_SCLK I2S_LRCLK In slave mode I2S_LRCLK In master mode I2S_SCLK I2S_DIN I2S_DOUT I2S_LRCLK SGTL5000 EA2 DS-0-3 Table 1-1. Min 10 Ti2s_s 1/Fsclk Ti2s_d Ti2s_s Ti2s_h Ti2s_d 1/Flrclk Figure 4. I2S Interface Timing SGTL5000 ...
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SGTL5000 2. POWER CONSUMPTION Table 8: Power Consumption: VDDA=1.8V, VDDIO=1.8V Mode Playback (I2S->DAC->Headphone) Playback with DAP ((I2S->DAP->DAC- >Headphone) Playback/Record (I2S->DAC->Head- phone, ADC->I2S) Record (ADC->I2S) Analog playback, CODEC bypassed (LINEIN->HP) Standby, all analog power off Playback with PLL (I2S->DAC->HP) VDDD derived ...
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Table 9: Power Consumption: VDDA=3.3V, VDDIO=3.3V Mode Playback with PLL (I2S->DAC->HP) SGTL5000 EA2 DS-0-3 Current Consumption (mA) VDDD VDDA VDDIO 3.92 2.76 SGTL5000 Power(mW) 22.05 11 ...
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SGTL5000 3. PINOUT & PACKAGE INFO 3.1. Pinout 12 20QFN Pinout HP_R I2S_SCLK 2 HP_VGND I2S_LRCLK 3 VDDA SYS_MCLK 4 HP_L VDDIO 5 VAG MIC_BIAS GND Figure 5. SGTL5000 20QFN Pinout SGTL5000_20QFN SGTL5000_20QFN GND ...
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Pin Description Pin Pin Name Count 1 HP_R 2 HP_VGND 3 VDDA 4 HP_L 5 VAG 6 LINEOUT_R 7 LINEOUT_L 8 LINEIN_R 9 LINEIN_L 10 MIC 11 CPFILT 12 VDDIO 13 SYS_MCLK 14 I2S_LRCLK 15 I2S_SCLK 16 I2S_DOUT 17 ...
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SGTL5000 Pin Pin Name Count 1 GND 2 HP_R 3 GND 4 HP_VGND 5 VDDA 6 HP_L 7 AGND VAG 11 LINEOUT_R 12 LINEOUT_L 13 LINEIN_R 14 LINEIN_L 15 MIC 16 MIC_BIAS ...
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Pin Pin Name Count 27 CTRL_DATA CTRL_CLK 30 VDDD 31 CTRL_ADR0_CS 32 CTRL_MODE PAD GND 3.3. Package SGTL5000 EA2 DS-0-3 Table 11. 32 pin QFN pinout Description I2C Mode: Serial Data (SDA); SPI Mode: Serial Data Input ...
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SGTL5000 16 SGTL5000 EA2 DS-0-3 ...
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SGTL5000 EA2 DS-0-3 SGTL5000 17 ...
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SGTL5000 18 SGTL5000 EA2 DS-0-3 ...
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TYPICAL CONNECTION DIAGRAMS Typical connection diagrams are shown in this section that demonstrate the flexibil- ity of the SGTL5000. Both low cost and low power configurations are presented although it should be noted that all configurations offer a low ...
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SGTL5000 5 4 20QFN Typical Connection Diagram Audio Jack Audio Jack VDDA (1.62V to 3.6V .1uF .1uF Notes: 1. The above circuit shows VDDD (pin 20) being derived internally. For lowest ...
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C2 C2 220uF 220uF 220uF 220uF Audio Jack Audio Jack VDDA (=1.6V 0.1uF 0.1uF C6 C6 .1uF .1uF LINE_OUT_RIGHT LINE_OUT_LEFT 20QFN Typical Connection Diagram - Lowest Power Configuration SGTL5000 ...
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SGTL5000 Audio Jack Audio Jack VDD (=3.1V to 3.6V 0.1uF 0.1uF SGTL5000_32QFN SGTL5000_32QFN 5 LINE_OUT_R 5 LINE_OUT_L Notes: 1. VDDD is derived internally (no need for external cap) 2. VDDA and ...
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C2 C2 220uF 220uF 220uF 220uF Audio Jack Audio Jack VDDA (=1.6V 0.1uF 0.1uF 5 LINE_OUT_R 5 LINE_OUT_L 32QFN Typical Connection Diagram - Lowest Power Configuration ...
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SGTL5000 C2 C2 220uF 220uF 220uF 220uF Audio Jack Audio Jack VDDA (=1.6V 0.1uF 0.1uF C6 C6 .1uF .1uF LINE_OUT_RIGHT LINE_OUT_LEFT 20QFN Typical Connection Diagram - Lowest Power Configuration ...
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Typical Connection Diagram Audio Jack Audio Jack Notes: 1. The above circuit shows VDDD (pin 30) being derived internally. For lowest power operation VDDD can be driven from an external 1.2V supply with ...
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SGTL5000 5. DEVICE DESCRIPTION The SGTL5000 is a low power stereo codec with integrated headphone amplifier designed to provide a complete audio solution for portable products needing line- in, mic-in, line-out, headphone-out, and digital I/O. Deriving it’s architecture ...
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System Block Diagram w/ Signal Flow and Gain Map Figure 10 below shows a block diagram that highlights the signal flow and gain map for the SGTL5000. LINE_IN Analog Gain MIC GAIN (0 to MIC_IN (0dB, 20dB, 22.5dB) 30dB, ...
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SGTL5000 Note that if VDDA and VDDIO are derived from the same voltage, a single decou- pling capacitor can be used to minimize cost. This capacitor should be placed clos- est to VDDA. • VDDD: This is a digital power ...
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Clocking Clocking for the SGTL5000 is provided by a system master clock input (SYS_MCLK). SYS_MCLK should be synchronous to the sampling rate (Fs) of the I2S port. Alternatively any clock between 8Mhz and 27Mhz can be provided on SYS_MCLK ...
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SGTL5000 CHIP_CLK_TOP _CTRL->INPUT_FREQ_DIV2 = 1 PLL_INPUT_FREQ = SYS_MCLK/2 PLL_OUTPUT_FREQ=180 .6336 MHz CHIP_PLL_CTRL->INT_DIVISOR = FLOOR (PLL_OUTPUT_FREQ/INPUT_FREQ CHIP_PLL_CTRL->FRAC_DIVISOR = ((PLL_OUTPUT_FREQ/INPUT_FREQ) - INT_DIVISOR) * 2048 For example, when a 12MHz digital signal is placed on MCLK, for a 48kHz frame clock CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = ...
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To configure a route, the CHIP_SSS_CTRL register is used. Each output from the source select switch has its own register field that is used to select what input is routed to that output. For example, to route the I2S digital ...
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SGTL5000 The ADC has an available Zero-Cross Detect (ZCD) that will prevent any volume change until a zero-volt crossing of the audio signal is detected. This helps in elimi- nating pop or other audio anomalies. If the ADC is to ...
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The lineout volume is intended as maximum output level adjustment intended to be used to set the maximum output swing. It does not have the range of a typical volume control and does not have a zero cross ...
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SGTL5000 I2S Format (n = bit length) CHIP_I2S0_CTRL field values: (SCLKFREQ = 0; SCLK_INV = 0; DLEN = 1; I2S_MODE = 0; LRALIGN = 0; LRPOL = 0) I2S_LRCLK I2S_SCLK I2S_DIN, DOUT (n-1) Left Justified Format (n ...
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PCM Format A signifies the data word beginning one SCLK bit following the I2S_LRCLK transition I2S Mode. PCM Format B signifies the data word begin- ning after the I2S_LRCLK transition Left Justified. In Slave mode, the ...
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SGTL5000 The block diagram in Figure 14 shows the sequence in which the signal passes through these blocks. Set DAP_CONTROL->DAP_EN to enable DAP block Main Input From Automatic Dual Source Volume Input Select Control Mixer Swtich (AVC) Mix Input Each ...
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DAP_MAIN_CHAN->VOL Main Channel From Source Select Switch Mix Channel From Source Select Switch The Dual Input Mixer can be enabled or configured in a pass-through mode (Main channel will be passed through without any mixing). When enabled, the volume of ...
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SGTL5000 Please refer to section 6.2.4.2 and section 6.3.5 for a programming example on how to configure Surround width and how to enable/disable Surround. 5.9.3. SigmaTel Bass Enhance SigmaTel Bass Enhance is a royalty-free algorithm that enhances natural bass response ...
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The 7-band PEQ allows the designer to compensate for speaker response and to provide the ability to filter out resonant frequencies caused by the physical system design. The system designer can create custom EQ presets such Rock, Speech, Classical ...
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SGTL5000 Please refer to section 6.3.2 for a programming example that shows how load the fil- ter coefficients when the end-user changes the preset. PEQ can be disabled (pass-through mode) by writing 0 to DAP_AUDIO_EQ->EN bits. 5.9.4.2. The 5-band graphic ...
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When the measured audio level is below threshold, the AVC can apply a maximum gain 12dB. The maximum gain can be selected, either 12dB. When the maximum gain is set to 0dB the AVC ...
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SGTL5000 • Send two bytes for the 16 bits of data to be written to the register (most signifi- cant byte first) • Stop condition An I2C read transaction is defined as follows: • Start condition • Device address with ...
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S Device W A Address (0) S Device W A Address (0) S Device W A start Address (0) ADDR byte 1 Table 17. Read Continuing Auto increment S Device R Address 5.10.2. SPI Serial Peripheral Interface (SPI ...
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SGTL5000 6. PROGRAMMING EXAMPLES This section provides programming examples that show how to configure the chip. The registers can be written/read by using I2C communication protocol. The chip also supports SPI communication protocol but only register write operation is sup- ...
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Chip Configuration All outputs (LINEOUT, HP_OUT, I2S_OUT) are muted by default on powerup. To avoid any pops/clicks, the outputs should remain muted during these chip configura- tion steps. Refer to section 6.2.6 for volume and mute control. 6.2.1. Initialization ...
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SGTL5000 // to 75mA Write CHIP_SHORT_CTRL // Enable Zero-cross detect if needed for HP_OUT (bit 5) and ADC (bit 1) Write CHIP_ANA_CTRL //----------------Power up Inputs/Outputs/Digital Blocks------------- // Power up LINEOUT, HP, ADC, DAC Write CHIP_ANA_POWER // Power up desired digital ...
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Set the PLL dividers Int_Divisor = floor(PLL_Output_Freq/Sys_MCLK_Input_Freq) Frac_Divisor = ((PLL_Output_Freq/Sys_MCLK_Input_Freq) - Int_Divisor)*2048 Modify CHIP_PLL_CTRL->INT_DIVISOR Int_Divisor Modify CHIP_PLL_CTRL->FRAC_DIVISOR Frac_Divisor 6.2.3. Input/Output Routing To avoid any pops/clicks, the outputs should be muted during these chip configura- tion steps. Refer to section ...
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SGTL5000 Write DAP_MAIN_CHAN 0x4000 // Configure mix channel volume to 50% (attenuate the mix // input level by half) Write DAP_MIX_CHAN 0x4000 6.2.4.2. The SigmaTel Surround on/off function will be typically controlled by the end-user. End-user driven programming steps are ...
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The AVC on/off function will be typically controlled by the end-user. End-user driven programming steps are shown in section 6.3. The default configuration of the AVC should work for most applications. However, the following example shows how to change ...
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SGTL5000 Write CHIP_DAC_VOL 0x3C3C Modify CHIP_ADCDAC_CTRL->DAC_MUTE_LEFT 0x0000 Modify CHIP_ADCDAC_CTRL->DAC_MUTE_RIGHT 0x0000 // Unmute ADC Modify CHIP_ANA_CTRL->MUTE_ADC 0x0000 6.3. End-user Driven Chip Configuration End-users will control features like volume up/down, audio EQ parameters such as Bass and Treble. This will require programming ...
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GEQ volume should be ramped in 0.5 dB steps in order to avoid any pops. The example assumes that volume is ramped on Band 0. Other bands can be pro- grammed similiarly. // Read current volume set on Band 0 ...
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SGTL5000 // Read current Surround width value // WIDTH_CONTROL bits 6:4 usOriginalVal = (Read DAP_SGTL_SURROUND >> 4) && 0x0003; usNextVal = usOriginalVal; // Ramp up the width to maximum value of 7 for (int i++; (7 - ...
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Automatic Volume Control (AVC) On/Off This programming example shows how to program the AVC on/off when end-user turns it on/off on his device. // Enable AVC (To disable, write 0x0000) Modify DAP_AVC_CTRL->EN 0x0001 SGTL5000 EA2 DS-0-3 SGTL5000 // bit ...
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SGTL5000 7. REGISTER DESCRIPTION 7.0.0. BITS FIELD 15:8 PARTID 7:0 REVID 7.0.0. BITS FIELD 15:7 RSVD 6 ADC_POWERUP 5 DAC_POWERUP 4 DAP_POWERUP 3:2 RSVD 1 I2S_OUT_POWE RUP 0 I2S_IN_POWERU P 54 CHIP_ID ...
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BITS FIELD 15:6 RSVD 5:4 RATE_MODE 3:2 SYS_FS 1:0 MCLK_FREQ 7.0.0. BITS FIELD 15:9 RSVD SGTL5000 EA2 DS-0-3 CHIP_CLK_CTRL 0x0004 RESET RO 0x0 Reserved ...
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SGTL5000 BITS FIELD 8 SCLKFREQ SCLK_INV 5:4 DLEN 3:2 I2S_MODE 1 LRALIGN 0 LRPOL 7.0.0. BITS FIELD 15 RSVD 56 RW RESET 0x0 Sets frequency of I2S_SCLK when in master mode (MS=1). RW ...
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BITS FIELD 14 DAP_MIX_LRSW AP 13 DAP_LRSWAP 12 DAC_LRSWAP 11 RSVD 10 I2S_LRSWAP 9:8 DAP_MIX_SELEC T 7:6 DAP_SELECT 5:4 DAC_SELECT 3:2 RSVD 1:0 I2S_SELECT 7.0.0. SGTL5000 EA2 DS-0-3 RW RESET 0x0 DAP Mixer Input Swap RW ...
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SGTL5000 BITS FIELD 15:14 RSVD 13 VOL_BUSY_DAC _RIGHT 12 VOL_BUSY_DAC _LEFT 11:10 RSVD 9 VOL_RAMP_EN 8 VOL_EXPO_RAM P 7:4 RSVD 3 DAC_MUTE_RIG HT 2 DAC_MUTE_LEF T 1 ADC_HPF_FREE ZE 0 ADC_HPF_BYPA SS 7.0.0. RESET ...
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BITS FIELD 15:8 DAC_VOL_RIGH T 7:0 DAC_VOL_LEFT 7.0.0. BITS FIELD 15:14 RSVD 9:8 I2S_LRCLK 7:6 I2S_SCLK SGTL5000 EA2 DS-0-3 RW RESET 0x3C DAC Right Channel Volume RW Set the Right channel DAC volume with 0.5017 dB ...
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SGTL5000 BITS FIELD 5:4 I2S_DOUT 3:2 CTRL_DATA 1:0 CTRL_CLK 7.0.0. BITS FIELD 15:9 RSVD 8 ADC_VOL_M6DB RW 7:4 ADC_VOL_RIGH RESET 0x1 I2C DOUT Pad Drive Strength RW Sets drive strength for output pads ...
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BITS FIELD 3:0 ADC_VOL_LEFT 7.0.0.10. CHIP_ANA_HP_CTRL BITS FIELD 15 RSVD 14:8 HP_VOL_RIGHT 7 RSVD 6:0 HP_VOL_LEFT 7.0.0.11. This is an analog control register that includes mutes, input selects, and zero-cross- detectors for the ADC, headphone, and ...
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SGTL5000 BITS FIELD 15:9 RSVD 8 MUTE_LO 7 RSVD 6 SELECT_HP 5 EN_ZCD_HP 4 MUTE_HP 3 RSVD 2 SELECT_ADC 1 EN_ZCD_ADC 0 MUTE_ADC 7.0.0.12. CHIP_LINREG_CTRL This register controls the VDDD linear regulator and the charge pump ...
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BITS FIELD 5 VDDC_ASSN_OV RD 4 RSVD 3:0 D_PROGRAMMI NG 7.0.0.13. CHIP_REF_CTRL This register controls the bandgap reference bias voltage and currents BITS FIELD 15:9 RSVD 8:4 VAG_VAL 3:1 BIAS_CTRL 0 SMALL_POP SGTL5000 EA2 DS-0-3 RW ...
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SGTL5000 7.0.0.14. CHIP_MIC_CTRL This register controls the microphone gain and the internal microphone biasing cir- cuitry BITS FIELD 15:10 RSVD 9:8 BIAS_RESISTOR 7 RSVD 6:4 BIAS_VOLT 3:2 RSVD 1:0 GAIN 7.0.0.15. CHIP_LINE_OUT_CTRL ...
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BITS FIELD 15:12 RSVD 11:8 OUT_CURRENT 7:6 RSVD 5:0 LO_VAGCNTRL 7.0.0.16. CHIP_LINE_OUT_VOL BITS FIELD 15:13 RSVD 12:8 LO_VOL_RIGHT 7:5 RSVD 4:0 LO_VOL_LEFT SGTL5000 EA2 DS-0-3 RW RESET 0x0 Reserved RO RW 0x0 Controls the output bias ...
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SGTL5000 Table 18. Line Out Output Level Values VDDA VAG_VAL 1.8V 0.9 1.8V 0.9 3.3V 1.55 3.3V 1.55 7.0.0.17. CHIP_ANA_POWER This register contains all of the powerdown controls for the analog blocks. The only other powerdown controls are BIAS_RESISTOR in ...
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BITS FIELD 11 VDDC_CHRGPM P_POWERUP 10 PLL_POWERUP 9 LINREG_D_POW ERUP 8 VCOAMP_POWE RUP 7 VAG_POWERUP 6 ADC_MONO 5 REFTOP_POWE RUP 4 HEADPHONE_P OWERUP 3 DAC_POWERUP 2 CAPLESS_HEAD PHONE_POWER UP SGTL5000 EA2 DS-0-3 RW RESET 0x0 Power up the VDDC chargepump ...
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SGTL5000 BITS FIELD 1 ADC_POWERUP 0 LINEOUT_POWE RUP 7.0.0.18. CHIP_PLL_CTRL This register may only be changed after reset, and before PLL_POWERUP is set BITS FIELD 15:11 INT_DIVISOR 10:0 FRAC_DIVISOR 68 RW RESET 0x0 Power up the ...
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CHIP_CLK_TOP_CTRL Miscellaneous controls for the clock block BITS FIELD 15:12 RESERVED 11 ENABLE_INT_OS C 10:4 RSVD 3 INPUT_FREQ_DI V2 2:0 RSVD 7.0.0.20. CHIP_ANA_STATUS Status bits for analog blocks BITS FIELD 15:10 ...
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SGTL5000 BITS FIELD 4 PLL_IS_LOCKED 3:0 RSVD 7.0.0.21. CHIP_ANA_TEST1 These register controls are intended only for debug BITS FIELD 15:14 HP_IALL_ADJ 13:12 HP_I1_ADJ 11:9 HP_ANTIPOP 8 HP_CLASSAB 7 HP_HOLD_GND_ CENTER 6 HP_HOLD_GND 5 VAG_DOUB_CUR RENT 4 ...
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BITS FIELD 0 TESTMODE 7.0.0.22. CHIP_ANA_TEST2 BITS FIELD 15 RSVD 14 LINEOUT_TO_VD DA 13 SPARE 12 MONOMODE_DA C 11 VCO_TUNE_AGA IN 10 LO_PASS_MAST ERVAG 9 INVERT_DAC_SA MPLE_CLOCK 8 INVERT_DAC_D ATA_TIMING 7 DAC_EXTEND_R TZ 6 DAC_DOUBLE_I 5 ...
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SGTL5000 BITS FIELD 0 ADC_DITHEROF F 7.0.0.23. CHIP_SHORT_CTRL This register contains controls for the headphone short detectors BITS FIELD 15 RSVD 14:12 LVLADJR 11 RSVD 10:8 LVLADJL 7 RSVD 72 RW RESET 0x0 Turns off the ...
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BITS FIELD 6:4 LVLADJC 3:2 MODE_LR 1:0 MODE_CM SGTL5000 EA2 DS-0-3 RW RESET 0x0 These bits adjust the sensitivity of the capless headphone RW center channel short detector in 50mA steps. This trip point can vary by ~30% over process ...
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SGTL5000 7.0.0.24. DAP_CONTROL BITS FIELD 15:5 RSVD 4 MIX_EN 3:1 RSVD 0 DAP_EN 7.0.0.25. DAP_PEQ BITS FIELD 15:3 RSVD 2:0 EN 7.0.0.26. DAP_BASS_ENHANCE BITS FIELD 15:9 RSVD 74 ...
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BITS FIELD 8 BYPASS_HPF 7 RSVD 6:4 CUTOFF 3:1 RSVD 0 EN 7.0.0.27. DAP_BASS_ENHANCE_CTRL BITS FIELD 15:14 RSVD 13:8 LR_LEVEL 7 RSVD 6:0 BASS_LEVEL 7.0.0.28. DAP_AUDIO_EQ BITS FIELD 15:2 RSVD SGTL5000 EA2 ...
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SGTL5000 BITS FIELD 1:0 EN 7.0.0.29. DAP_SGTL_SURROUND BITS FIELD 15:7 RSVD 6:4 WIDTH_CONTRO L 3:2 RSVD 1:0 SELECT 7.0.0.30. DAP_FILTER_COEF_ACCESS BITS FIELD 15:9 RSVD RESET 0x0 Selects between ...
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BITS FIELD 7:0 INDEX 7.0.0.31. DAP_COEF_WR_B0_MSB BITS FIELD 15 BIT_19 14 BIT_18 13 BIT_17 12 BIT_16 11 BIT_15 10 BIT_14 9 BIT_13 8 BIT_12 7 BIT_11 6 BIT_10 5 BIT_9 4 BIT_8 3 BIT_7 2 BIT_6 ...
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SGTL5000 BITS FIELD 0 BIT_4 7.0.0.32. DAP_COEF_WR_B0_LSB BITS FIELD 15:4 RSVD 3 BIT_3 2 BIT_2 1 BIT_1 0 BIT_0 7.0.0.33. DAP_AUDIO_EQ_BASS_BAND0 115Hz BITS FIELD 15:7 RSVD 6:0 VOLUME 7.0.0.34. DAP_AUDIO_EQ_BAND1 330Hz 15 ...
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BITS FIELD 6:0 VOLUME 7.0.0.35. DAP_AUDIO_EQ_BAND2 990Hz BITS FIELD 15:7 RSVD 6:0 VOLUME 7.0.0.36. DAP_AUDIO_EQ_BAND3 3000Hz BITS FIELD 15:7 RSVD 6:0 VOLUME 7.0.0.37. DAP_AUDIO_EQ_TREBLE_BAND4 9900Hz SGTL5000 EA2 DS-0-3 ...
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SGTL5000 BITS FIELD 15:7 RSVD 6:0 VOLUME 7.0.0.38. DAP_MAIN_CHAN Sets the main channel volume level BITS FIELD 15:0 VOL 7.0.0.39. DAP_MIX_CHAN Sets the mix channel volume level BITS FIELD 15:0 VOL 7.0.0.40. ...
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BITS FIELD 13:12 MAX_GAIN 11:10 RSVD 9:8 LBI_RESPONSE 7:6 RSVD 5 HARD_LIMIT_EN 4:1 RSVD 0 EN 7.0.0.41. DAP_AVC_THRESHOLD BITS FIELD 15:0 THRESH 7.0.0.42. DAP_AVC_ATTACK BITS FIELD 15:12 RSVD SGTL5000 EA2 DS-0-3 RW ...
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SGTL5000 BITS FIELD 11:0 RATE 7.0.0.43. DAP_AVC_DECAY BITS FIELD 15:12 RSVD 11:0 RATE 7.0.0.44. DAP_COEF_WR_B1_MSB BITS FIELD 15:0 MSB 82 RW RESET 0x28 AVC Attack Rate RW This is the rate at ...
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DAP_COEF_WR_B1_LSB BITS FIELD 15:4 RSVD 3:0 LSB 7.0.0.46. DAP_COEF_WR_B2_MSB BITS FIELD 15:0 MSB 7.0.0.47. DAP_COEF_WR_B2_LSB BITS FIELD 15:4 RSVD 3:0 LSB 7.0.0.48. DAP_COEF_WR_A1_MSB ...
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SGTL5000 7.0.0.49. DAP_COEF_WR_A1_LSB BITS FIELD 15:4 RSVD 3:0 LSB 7.0.0.50. DAP_COEF_WR_A2_MSB BITS FIELD 15:0 MSB 7.0.0.51. DAP_COEF_WR_A2_LSB BITS FIELD 15:4 RSVD 3:0 LSB ...