SGTL5000XNLA3R2 Freescale Semiconductor, SGTL5000XNLA3R2 Datasheet - Page 29

• Manufacturer Part Number: SGTL5000XNLA3R2
• Description: IC AUDIO CODEC STEREO 20-QFN
• Manufacturer: Freescale Semiconductor
• Type: Stereo Audior

Specifications of SGTL5000XNLA3R2

• Data Interface: I²C, Serial, SPI™
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 90 / 100
• Voltage - Supply, Analog: 1.62 V ~ 3.6 V
• Voltage - Supply, Digital: 1.1 V ~ 2 V, 1.62 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-UFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SGTL5000 EA2 DS-0-3
System Master Clock (SYS_MCLK)
Sampling Frequency (Fs)
5.4.
note 1. For a sampling frequency of 96kHz, only 256Fs SYS_MCLK is supported
Clocking
5.4.1.
5.4.2.
Clock
Clocking for the SGTL5000 is provided by a system master clock input
(SYS_MCLK). SYS_MCLK should be synchronous to the sampling rate (Fs) of the
I2S port. Alternatively any clock between 8Mhz and 27Mhz can be provided on
SYS_MCLK and the SGTL5000 can use an internal PLL to derive all internal and
I2S clocks. This allows the system to use an available clock such as 12MHz (com-
mon USB clock) for SYS_MCLK to reduce overall system costs.
Synchronous SYS_MCLK input
The SGTL5000 supports various combinations of SYS_MCLK frequency and sam-
pling frequency as shown in Table 12. Using a synchronous SYS_MCLK allows for
lower power as the internal PLL is not used.
Using the PLL - Asynchronous SYS_MCLK input
An integrated PLL is provided in the SGTL5000 that allows any clock from 8MHz to
27MHz to be connected to SYS_MCLK. This can help save system costs as a clock
available elsewhere in the system can be used to derive all audio clocks using the
internal PLL. In this case the clock input to SYS_MCLK can be asynchronous with
the sampling frequency needed in the system. For example a 12MHz clock from the
system processor could be used as the clock input to the SGTL5000.
Three register fields need to be configured to properly use the PLL. They are
CHIP_PLL_CTRL->INT_DIVISOR,
CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2. Figure 11 shows a flowchart that
shows how to determine the values to program in the register fields.
Table 12. Synchronous MCLK Rates
256, 384, 512
8, 11.025, 16, 22.5, 32, 44.1, 48,
96(note 1)
Supported rates
CHIP_PLL_CTRL->FRAC_DIVISOR
Fs
kHz
SGTL5000
Units
and
29