SGTL5000XNLA3R2 Freescale Semiconductor, SGTL5000XNLA3R2 Datasheet - Page 42

• Manufacturer Part Number: SGTL5000XNLA3R2
• Description: IC AUDIO CODEC STEREO 20-QFN
• Manufacturer: Freescale Semiconductor
• Type: Stereo Audior

Specifications of SGTL5000XNLA3R2

• Data Interface: I²C, Serial, SPI™
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 90 / 100
• Voltage - Supply, Analog: 1.62 V ~ 3.6 V
• Voltage - Supply, Digital: 1.1 V ~ 2 V, 1.62 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-UFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SGTL5000
42
Start Condition
S
I2C Address
Address
Device
•
•
An I2C read transaction is defined as follows:
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•
•
•
•
•
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Figure 19 shows the functional I2C timing diagram.
The protocol has an auto increment feature. Instead of sending the stop condition
after two bytes of data, the master may continue to send data byte pairs for writing,
or it may send extra clocks for reading data byte pairs. In either case, the access
address is incremented after every two bytes of data. A start or stop condition from
the I2C master interrupts the current command. For reads, unless a new address is
written, a new start condition with R/W=0 reads from the current address and contin-
ues to auto increment.
The following diagrams describe the different access formats. The gray fields are
from the I2C master, and the white fields are the SGTL5000 responses. Data[n] cor-
responds to the data read from the address sent, data[n+1] is the data from the next
register, and so on.
S = Start Condition
Sr = Restart Condition
A = Ack
N = Nack
P = Stop Condition
TA2 silicon will allow for up to a 3.6V I2C signal level, regardless of the VDDIO level.
Send two bytes for the 16 bits of data to be written to the register (most signifi-
cant byte first)
Stop condition
Start condition
Device address with the R/W bit cleared to indicate write
Send two bytes for the 16 bit register address (most significant byte first)
Stop Condition followed by start condition (or a single restart condition)
Device address with the R/W bit set to indicate read
Read two bytes from the addressed register (most significant byte first)
Stop condition
R/W ACK
(0)
W
Figure 19. Functional I2C Diagram
A15
Table 13. Write Single Location
A
ADDR
byte 1
A8
ACK
A7
A
ADDR
byte 0
A0
ACK
A
D15
byte 1
DATA
D8
SGTL5000 EA2 DS-0-3
ACK
A
D7
Stop Condition
byte 0
DATA
D0
A
ACK
P