SGTL5000XNLA3R2 Freescale Semiconductor, SGTL5000XNLA3R2 Datasheet - Page 64

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SGTL5000XNLA3R2

Manufacturer Part Number
SGTL5000XNLA3R2
Description
IC AUDIO CODEC STEREO 20-QFN
Manufacturer
Freescale Semiconductor
Type
Stereo Audior
Datasheet

Specifications of SGTL5000XNLA3R2

Data Interface
I²C, Serial, SPI™
Number Of Adcs / Dacs
1 / 1
Sigma Delta
No
S/n Ratio, Adcs / Dacs (db) Typ
90 / 100
Voltage - Supply, Analog
1.62 V ~ 3.6 V
Voltage - Supply, Digital
1.1 V ~ 2 V, 1.62 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-UFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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SGTL5000
64
BITS
15:10
15
15
9:8
6:4
3:2
1:0
7
14
BIAS_RESISTOR
14
BIAS_VOLT
7.0.0.14. CHIP_MIC_CTRL
This register controls the microphone gain and the internal microphone biasing cir-
cuitry.
7.0.0.15. CHIP_LINE_OUT_CTRL
FIELD
RSVD
RSVD
RSVD
GAIN
13
13
12
12
RW RESET
RW
RW
RW
RO
RO
RO
11
11
0x0
0x0
0x0
0x0
0x0
0x0
10
10
9
Reserved
MIC Bias Output Impedance Adjustment
Controls an adjustable output impedance for the microphone
bias. If this is set to zero the micbias block is powered off and
the output is highZ.
0x0 = Powered off
0x1 = 2Kohm
0x2 = 4Kohm
0x3 = 8Kohm
Reserved
MIC Bias Voltage Adjustment
Controls an adjustable bias voltage for the microphone bias
amp in 250mV steps. This bias voltage setting should be no
more than VDDA-200mV for adequate power supply rejection.
0x0 = 1.25V
...
0x7 = 3.00V
Reserved
MIC Amplifier Gain
Sets the microphone amplifier gain. At 0dB setting the THD
can be slightly higher than other paths- typically around
~65dB. At other gain settings the THD will be better.
0x0 = 0dB
0x1 = +20dB
0x2 = +30dB
0x3 = +40dB
9
8
8
7
7
0x002A
6
6
0x002C
DEFINITION
5
5
4
4
SGTL5000 EA2 DS-0-3
3
3
2
2
1
1
0
0

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