SGTL5000XNLA3R2 Freescale Semiconductor, SGTL5000XNLA3R2 Datasheet - Page 46

• Manufacturer Part Number: SGTL5000XNLA3R2
• Description: IC AUDIO CODEC STEREO 20-QFN
• Manufacturer: Freescale Semiconductor
• Type: Stereo Audior

Specifications of SGTL5000XNLA3R2

• Data Interface: I²C, Serial, SPI™
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 90 / 100
• Voltage - Supply, Analog: 1.62 V ~ 3.6 V
• Voltage - Supply, Digital: 1.1 V ~ 2 V, 1.62 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-UFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SGTL5000
46
6.2.2.
// to 75mA
Write CHIP_SHORT_CTRL
// Enable Zero-cross detect if needed for HP_OUT (bit 5) and ADC (bit 1)
Write CHIP_ANA_CTRL
//----------------Power up Inputs/Outputs/Digital Blocks-------------
// Power up LINEOUT, HP, ADC, DAC
Write CHIP_ANA_POWER
// Power up desired digital blocks
// I2S_IN (bit 0), I2S_OUT (bit 1), DAP (bit 4), DAC (bit 5),
// ADC (bit 6) are powered on
Write CHIP_DIG_POWER
//--------------------Set LINEOUT Volume Level-----------------------
// Set the LINEOUT volume level based on voltage reference (VAG)
// values using this formula
// Value = (int)(40*log(VAG_VAL/LO_VAGCNTRL) + 15)
// Assuming VAG_VAL and LO_VAGCNTRL is set to 0.9V and 1.65V respectively, the
// left LO vol (bits 12:8) and right LO volume (bits 4:0) value should be set
// to 5
Write CHIP_LINE_OUT_VOL
6.2.1.2.
// Configure SYS_FS clock to 48kHz
// Configure MCLK_FREQ to 256*Fs
Modify CHIP_CLK_CTRL->SYS_FS 0x0002
Modify CHIP_CLK_CTRL->MCLK_FREQ 0x0000
// Configure the I2S clocks in master mode
// NOTE: I2S LRCLK is same as the system sample clock
Modify
PLL Configuration
These programming steps are needed only when the PLL is used. Please refer to
section 5.4.2 for details on when to use the PLL.
To avoid any pops/clicks, the outputs should be muted during these chip configura-
tion steps. Refer to section 6.2.6 for volume and mute control.
// Power up the PLL
Modify
Modify
// NOTE:
// is above 17MHz. In this case the external SYS_MCLK clock
// must be divided by 2
Modify
Sys_MCLK_Input_Freq = Sys_MCLK_Input_Freq/2;
// PLL output frequency is different based on the sample clock
// rate used.
if (Sys_Fs_Rate == 44.1kHz)
else
PLL_Output_Freq = 180.6336MHz
PLL_Output_Freq = 196.608MHz
CHIP_I2S_CTRL->MS
CHIP_ANA_POWER->PLL_POWERUP
CHIP_ANA_POWER->VCOAMP_POWERUP
CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2
This step is required only when the external SYS_MCLK
System MCLK and Sample Clock
0x1106
0x0001
0x0133
0x6AFF
0x0073
0x0505
// bit 7
// bits 3:2
0x0001
// bits 1:0
0x0001
0x0001
// bit 10
// bit 8
// bit 3
SGTL5000 EA2 DS-0-3