MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 97

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

3
3.2.9 S y s t e m Control Instructions
3-12
Table 3-9 summarizes these instructions. The TRAPcc instruction uses the
same conditional tests as the corresponding program control instructions.
All of these instructions cause the processor to flush the instruction pipe.
Privileged instructions, trapping instructions, and instructions that use or
modify the condition code register (CCR) provide system control operations.
ANDI
CHK
TRAP
TRAPcc
TRAPV
ANDI
EORI
ORI
EORI
MOVE
MOVE
MOVEC
MOVES
ORI
RESET
RTE
STOP
BKPT
CHK2
ILLEGAL
MOVE
Instruction
I Operand Syntax
#<data>,CCR
#<data>,CCR
#<data>,CCR
#<data>,SR
#<data>,SR
#<data>,SR
<ea>,CCR
CCR,<ea>
#<data>
#<data>
#<data>
#<data>
<ea>,SR
SR,<ea>
Rn,<ea>
<ea>,Rn
<ea>,Dn
<ea>,Rn
USP,An
An,USP
Rc,Rn
Rn,Rc
none
none
none
none
none
Table 3-9. System Control Operations
MC68030 USER'S
Operand Size I
8,16,32
8,16,32
Condition Code Register
16,32
none
none
none
16,32
none
none
none
none
32
32
32
32
16
16
16
16
16
16
16
16
8
8
8
Trap Generating
Privileged
An i USP
SSP - 2 I) SSP; Format and Vector Offset 0 (SSP)
source $ CCR
CCR J destination
immediate data ® SR 0 SR
source $ SR
SR $ destination
USP $ An
Rc $ Rn
Rn $ Rc
Rn 0 destination using DFC
source using SFC $ Rn
immediate data V SR $ SR
(SP) i SR; SP+2 i SP; (SP) 0 PC; SP+4 J SP;
immediate data I) SR; STOP
run breakpoint cycle, then trap as illegal instruction
if Dn<0 or Dn>(ea), then CHK excep,tion
if Rn<lower bound or Rn>upper bound, the CHK
SSP - 2 I) SSP; Vector Offset i) (SSP);
SSP - 4 ~ SSP; PC J (SSP);
SSP - 2 I) SSP; SR I) (SSP);
Illegal Instruction Vector Address t PC
SSP - 4 J SSP; PC ~ (SSP); SSP - 2 i SSP;
SR t (SSP); Vector Address I) PC
if cc true, then TRAP exception
if V then take overflow TRAP exception
immediate data A SR j SR
assert RESET line
immediate data (~ CCR t CCR
immediate data V CCR ~ CCR
immediate data A CCR 0 CCR
M A N U A L
exception
Restore stack according to format
Operation
M O T O R O L A