MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 142

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
ih
Ill
CACHE SIZE = 64 (LONG WORDS)
LINE SIZE = 4 (LONG WORDS)
SET SIZE = 1
When enabled, the instruction cache is used to store instruction prefetches
dresses except when a change of program flow occurs (e.g., a branch taken)
or when an instruction is executed that can modify the status register, in
which cases the instruction pipe is automatically flushed and refilled. The
tinguish between user and supervisor accesses), and the four valid bits (one
(instruction words and extension words) as they are requested by the CPU.
Instruction prefetches are normally requested from sequential memory ad-
output signal REFILL indicates this condition. For more information on the
operation of this signal, refer to SECTION 12 APPLICATIONS INFORMATION.
In the instruction cache, each of the 16 lines has a tag consisting of the 24
most significant logical address bits, the FC2 function code bit (used to dis-
1
A . . . A A A A A A A A A A A A A A A A A A A A A A
3 . . . 2
1ooo3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
REPLACE
TAG
1 OF 16 /
SELECT ~
Figure 6-2. On-Chip Instruction Cache Organization
TAG
I
t
I
COMPARATOR
MC68030 USER'S MANUAL
~
TA6
,~
-3
,
t _ _ l
V V V V
•
II 1.
II I IIII
•
VAUD
,NOEX
•
•
LONG WORD
I~--]
SELECT
!
t
A
0
0
ENTRY HIT
ACCESS ADDRESS
L . _ _ ~ CACHE HOLDING REGISTER
T ~
DATA FROM INSTRUCTON
CACHE DATA BUS
DATA TO INSTRUCTION
CACHE CONTROL LOGIC
6-5