MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 556

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
to retry the cycle (two clocks during which the miss is detected and two
Additionally, the degree of parallelism in the system should be considered.
terminated only after validation, use of the synchronous bus is recommended
the address-valid-to-DSACK-asserted timing for bus cycles of the same length.
the synchronous two-clock protocol, but most statements also apply to the
tion (TTx) registers). These two modes of operation, logical and physical,
time the logical-to-physical mapping of the system changes (as occurs during
clocks idle bus time), assuming that the bus control strobes (BERR and HALT)
are negated soon enough after the completion of the aborted cycle that the
cache miss rate determines the percentage of cycles that must be retried.
while the processor is retrying the cycle, it is possible to avoid some, or all,
of the performance penalty associated with late retry (although the control
circuitry required may be more complex).
dated, but for a three or more clock, nonburst cache, the choice of synchron-
ous versus asynchronous operation must be made. If the bus cycle is
since the address-valid-to-STERM-asserted timing requirement is longer than
structures. Some external caches might use both synchronous and asyn-
chronous transfers: synchronous for hits and asynchronous for misses or
vice versa. The following discussion assumes that the external cache uses
asynchronous protocol.
directly mapped logical-to-physical addresses from the transparent transla-
affect the maintenance of external caches. For example, when the external
cache uses physical addresses, the cache need not be flushed on each context
the logical address space, a logical cache must be flushed of all entries any
a context switch). Since there is only a single physical address space, this
The intended cache size should be evaluated when considering the utility of
fill the cache and remove all entries created during the execution of previous
next cycle can begin immediately. In evaluating this overhead, the projected
If, after a cache miss, it is possible to continue the bus cycle to main memory
For a two-clock bus or burst capability, use of the synchronous bus is man-
If the cache implements late retry, the choice of which bus control mode to
use is less important and depends on system-specific features and control
If the MC68030 MMU is disabled, all bus cycles use logical addresses. If the
MMU is enabled, the external address bus uses physical addresses (including
switch. Since each task in a system may have its own unique mapping of
problem does not occur with a physical cache because all references to a
particular operand must utilize the same physical address.
allowing multiple tasks to maintain cache entries. If the cache is relatively
small and the time between context switches is large, each task will tend to
MC68030 USER'S MANUAL
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