MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 272

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

8.1.1 Reset E x c e p t i o n
MOTOROLA
Assertion by external hardware of the RESE-I = signal causes a reset exception.
The reset exception has the highest priority of any exception; it provides for
system initialization and recovery from catastrophic failure. When reset is
the following operations:
After the initial instruction prefetches, program execution begins at the ad-
dress in the program counter. The reset exception does not flush the address
translation cache (ATC), nor does it save the value of either the program
counter or the status register.
OPERATION.
recognized, it aborts any processing in progress, and that processing cannot
be recovered. Figure 8-1 is a flowchart of the reset exception, which performs
For details on the requirements for the assertion of RESET, refer to 7.8 RESET
10. Loads the second long word of the reset exception vector into the
3. Sets the processor interrupt priority mask to the highest priority level
4. Initializes the vector base register to zero ($00000000).
6. Invalidates all entries in the instruction and data caches.
7. Clears the enable bit in the translation control register and the enable
8. Generates a vector number to reference the reset exception vector (two
9. Loads the first long word of the reset exception vector into the interrupt
2. Places the processor in the interrupt mode of the supervisor privilege
5. Clears the enable, freeze, and burst enable bits for both on-chip caches
1. Clears both trace bits in the status register to disable tracing.
level by setting the supervisor bit and clearing the master bit in the
status register.
(level 7).
and the write-allocate bit for the data cache in the cache control register.
bits in both transparent translation registers of the MMU.
long words) at offset zero in the supervisor program address space.
stack pointer.
program counter.
MC68030 USER'S MANUAL
8-5