MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 23

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

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Figure
Test Coprocessor Condition, Decrementand-Branch instruction
Trap on Coprocessor Condition (cpTRAPcc) ............................
Transfer Operation Word Primitive Format .............................
Transfer from Instruction Stream Primitive Format ..................
Write to Previously Evaluated Effective Address Primitive
Take Address and Transfer Data Primitive Format
Transfer To/From Top of Stack Primitive Format .....................
Transfer Single Main Processor Register Primitive Format ....... 10-50
Transfer Main Processor Control Register Primitive Format ...... 10-51
Transfer Multiple Coprocessor Registers Primitive Format ....... 10-53
Transfer Status Register and ScanPC Primitive Format .............
Take Pre-lnstruction Exception Primitive Format .....................
Coprocessor Interface Protocol for General Category
Coprocessor nterface Protocol for Conditional Category
Set on Coprocessor Condition (cpScc) ...................................
Coprocessor State Frame Format in Memory ..........................
Coprocessor Context Save Instruction Format (cpSAVE) ..........
Coprocessor Context Save Instruction Protocol .......................
Coprocesor Context Restore Instruction Format (cpRESTORE).. 10-27
Coprocessor Context Restore Instruction Protocol ...................
Control CIR Format ..............................................................
Condition CIR Format ............................................................
Operand Alignment for Operand CIR Accesses .......................
Coprocessor Response Primitive Format ................................
Busy Primitive Format ..........................................................
Null Primitive Format ...........................................................
Supervisor Check Primitive Format ........................................
Evaluate and Transfer Effective Address Primitive Format ........
Evaluate Effective Address and Transfer Data Primitive Format
Transfer Multiple Main Processor Registers Primitive Format...
Operand Format in Memory for Transfer to - ( A n ) ..................
Branch on Coprocessor Condition
Branch on Coprocessor Condition Instruction (cpBcc.L) ...........
Register Select Mask Format ..................................................
Instructions ......................................................................
Instructions ......................................................................
Format (cpDBcc)
Format .............................................................................
LIST OF ILLUSTRATIONS (Continued)
MC68030 USER'S MANUAL
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Title
I n s t r u c t i o n
(cpBcc.W) ..........
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MOTOROLA
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