MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 244

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
the timing for this case.
When the processor recognizes a bus error condition, it terminates the current
the case in which neither DSACKx nor STERM is asserted. Figure 7-50 shows
the timing for a bus error that is asserted after DSACKx. Exceptions are taken
Electrical Specifications)
systems that have memory error detection and correction logic and by ex-
ternal cache memories.
The bus error signal is recognized during a bus cycle in any of the following
cases:
exception processing.) When BERR is asserted during a read cycle that sup-
an externally generated bus error, the data in the cache is not marked invalid.
In the second case, where BERR is asserted after DSACKx is asserted, BERR
must be asserted within specification #48 (refer to MC68030EC/D,
asserted and remain stable during the sample window, defined by specifi-
cations #27A and #47B, around the next falling edge of the clock after DSACKx
is recognized. If BERR is not stable at this time, the processor may exhibit
erratic behavior. BERR has priority over DSACKx. In this case, data may be
present on the bus, but may not be valid. This sequence may be used by
The assertion of BERR described in the third case (recognized after STERM)
of the clock, as defined by specifications #27A and #28A. Figure 7-51 shows
bus cycle in the normal way. Figure 7-49 shows the timing of a bus error for
in both cases. (Refer to 8.1.2 Bus Error Exception for details of bus error
plies data to either on-chip cache, the data in the cache is marked invalid.
However, when a write cycle that writes data into the data cache results in
has requirements similar to those described in the preceding paragraph.
BERR must be stable throughout the sample window for the next falling edge
• DSACKx (or STERM) and HALT are negated and BERR is asserted.
• HALT and BERR are negated and DSACKx is assertedl BERR is then
• BERR is asserted and recognized on the next falling clock edge following
the rising clock edge on which STERM is asserted and recognized (HALT
asserted within one clock cycle (HALT remains negated).
remains negated).
MC68030 USER'S MANUAL
for purely asynchronous operation, or it must be
MC68030
7-83
N